forked from M-Labs/artiq
coredevice/ad9914: adapt to new binary shift typing
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@ -243,9 +243,9 @@ class AD9914:
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# Enable autoclear phase accumulator and enables OSK.
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self.write(AD9914_REG_CFR1L, 0x2108)
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fud_time = now_mu() + int64(2) * self.write_duration_mu
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pow -= int32((ref_time_mu - fud_time) * self.sysclk_per_mu * int64(ftw) >> int64(32 - 16))
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pow -= int32((ref_time_mu - fud_time) * self.sysclk_per_mu * int64(ftw) >> (32 - 16))
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if phase_mode == PHASE_MODE_TRACKING:
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pow += int32(ref_time_mu * self.sysclk_per_mu * int64(ftw) >> int64(32 - 16))
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pow += int32(ref_time_mu * self.sysclk_per_mu * int64(ftw) >> (32 - 16))
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self.write(AD9914_REG_POW, pow)
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self.write(AD9914_REG_ASF, asf)
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@ -319,9 +319,9 @@ class AD9914:
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self.write(AD9914_GPIO, (1 << self.channel) << 1)
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self.write(AD9914_REG_DRGAL, int32(xftw) & 0xffff)
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self.write(AD9914_REG_DRGAH, int32(xftw >> int64(16)) & 0x7fff)
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self.write(AD9914_REG_DRGFL, int32(xftw >> int64(31)) & 0xffff)
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self.write(AD9914_REG_DRGFH, int32(xftw >> int64(47)) & 0xffff)
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self.write(AD9914_REG_DRGAH, int32(xftw >> 16) & 0x7fff)
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self.write(AD9914_REG_DRGFL, int32(xftw >> 31) & 0xffff)
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self.write(AD9914_REG_DRGFH, int32(xftw >> 47) & 0xffff)
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self.write(AD9914_REG_ASF, amplitude)
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self.write(AD9914_FUD, 0)
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@ -340,7 +340,7 @@ class AD9914:
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frequency (extended resolution mode).
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"""
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return round64(2.0*float(int64(2)**int64(62))*frequency/self.sysclk) & (
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(int64(1) << int64(63)) - int64(1))
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(int64(1) << 63) - int64(1))
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@portable
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def xftw_to_frequency(self, xftw: int64) -> float:
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