From 70edc9c5c61edcf802932bd3fe542d1518f938d7 Mon Sep 17 00:00:00 2001 From: mwojcik Date: Wed, 11 Jan 2023 11:56:21 +0800 Subject: [PATCH] test_write_underflow: decrease underflow delay --- artiq/gateware/drtio/core.py | 2 +- artiq/gateware/test/drtio/test_full_stack.py | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/artiq/gateware/drtio/core.py b/artiq/gateware/drtio/core.py index 434751ccc..1af7fa7b4 100644 --- a/artiq/gateware/drtio/core.py +++ b/artiq/gateware/drtio/core.py @@ -77,7 +77,7 @@ class DRTIOSatellite(Module): self.reset = CSRStorage(reset=1) self.reset_phy = CSRStorage(reset=1) self.tsc_loaded = CSR() - # master interface in the rtio domain + # master interface in the sys domain self.cri = cri.Interface() self.async_errors = Record(async_errors_layout) diff --git a/artiq/gateware/test/drtio/test_full_stack.py b/artiq/gateware/test/drtio/test_full_stack.py index e55bb536a..ecae7644b 100644 --- a/artiq/gateware/test/drtio/test_full_stack.py +++ b/artiq/gateware/test/drtio/test_full_stack.py @@ -227,16 +227,16 @@ class TestFullStack(unittest.TestCase): errors = yield from saterr.protocol_error.read() self.assertEqual(errors, 0) yield from csrs.underflow_margin.write(0) - tb.delay(100) + tb.delay(80) yield from tb.write(42, 1) - for i in range(12): + for i in range(21): yield errors = yield from saterr.protocol_error.read() underflow_channel = yield from saterr.underflow_channel.read() underflow_timestamp_event = yield from saterr.underflow_timestamp_event.read() self.assertEqual(errors, 8) # write underflow self.assertEqual(underflow_channel, 42) - self.assertEqual(underflow_timestamp_event, 100) + self.assertEqual(underflow_timestamp_event, 80) yield from saterr.protocol_error.write(errors) yield errors = yield from saterr.protocol_error.read()