forked from M-Labs/artiq
serwb: revert some changes (was breaking simulation)
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0a6d4ccd85
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@ -121,9 +121,9 @@ class _SerdesMasterInit(Module):
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If((delay_min == 0) |
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If((delay_min == 0) |
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(delay_max == (taps - 1)) |
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(delay_max == (taps - 1)) |
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((delay_max - delay_min) < taps//16),
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((delay_max - delay_min) < taps//16),
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# switch to next bitslip
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NextValue(delay_min_found, 0),
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NextValue(delay, taps - 1),
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NextValue(delay_max_found, 0),
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NextState("INC_DELAY_BITSLIP")
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NextState("WAIT_STABLE")
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).Else(
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).Else(
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NextValue(delay, 0),
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NextValue(delay, 0),
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serdes.rx_delay_rst.eq(1),
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serdes.rx_delay_rst.eq(1),
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@ -238,9 +238,9 @@ class _SerdesSlaveInit(Module, AutoCSR):
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If((delay_min == 0) |
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If((delay_min == 0) |
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(delay_max == (taps - 1)) |
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(delay_max == (taps - 1)) |
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((delay_max - delay_min) < taps//16),
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((delay_max - delay_min) < taps//16),
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# switch to next bitslip
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NextValue(delay_min_found, 0),
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NextValue(delay, taps - 1),
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NextValue(delay_max_found, 0),
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NextState("INC_DELAY_BITSLIP")
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NextState("WAIT_STABLE")
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).Else(
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).Else(
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NextValue(delay, 0),
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NextValue(delay, 0),
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serdes.rx_delay_rst.eq(1),
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serdes.rx_delay_rst.eq(1),
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@ -258,9 +258,9 @@ class _SerdesSlaveInit(Module, AutoCSR):
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serdes.tx_idle.eq(1)
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serdes.tx_idle.eq(1)
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)
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)
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fsm.act("SEND_PATTERN",
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fsm.act("SEND_PATTERN",
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If(~serdes.rx_comma,
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timer.wait.eq(1),
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timer.wait.eq(1),
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If(timer.done,
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If(timer.done,
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If(~serdes.rx_comma,
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NextState("READY")
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NextState("READY")
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)
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)
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),
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),
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