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coredevice.ttl: add missed int64 conversion.

This commit is contained in:
whitequark 2016-03-04 08:37:38 +00:00
parent 7ff0c89d51
commit 6e44c5424d
1 changed files with 1 additions and 1 deletions
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artiq/coredevice/ttl.py
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@ -238,7 +238,7 @@ class TTLClockGen:
# in RTIO cycles
self.previous_timestamp = int(0, width=64)
self.acc_width = 24
self.acc_width = int(24, width=64)
@portable
def frequency_to_ftw(self, frequency):