From 6e44c5424dbadc4d6ca36bcbb0a497cad92849ec Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Fri, 4 Mar 2016 08:37:38 +0000
Subject: [PATCH] coredevice.ttl: add missed int64 conversion.

---
 artiq/coredevice/ttl.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/artiq/coredevice/ttl.py b/artiq/coredevice/ttl.py
index b841bde28..2cd308f55 100644
--- a/artiq/coredevice/ttl.py
+++ b/artiq/coredevice/ttl.py
@@ -238,7 +238,7 @@ class TTLClockGen:
 
         # in RTIO cycles
         self.previous_timestamp = int(0, width=64)
-        self.acc_width = 24
+        self.acc_width = int(24, width=64)
 
     @portable
     def frequency_to_ftw(self, frequency):