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satman: fix targets without drtio routing

This commit is contained in:
mwojcik 2024-01-09 10:41:22 +08:00
parent c9e3771cd5
commit 6c0ff9a912
2 changed files with 14 additions and 5 deletions
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1
artiq/firmware/satman/main.rs
View File

@ -790,6 +790,7 @@ pub extern fn main() -> i32 {
kernelmgr.process_kern_requests(&mut router, &routing_table, rank, destination, &mut dma_manager); kernelmgr.process_kern_requests(&mut router, &routing_table, rank, destination, &mut dma_manager);
#[cfg(has_drtio_routing)]
if let Some((repno, packet)) = router.get_downstream_packet() { if let Some((repno, packet)) = router.get_downstream_packet() {
if let Err(e) = repeaters[repno].aux_send(&packet) { if let Err(e) = repeaters[repno].aux_send(&packet) {
warn!("[REP#{}] Error when sending packet to satellite ({:?})", repno, e) warn!("[REP#{}] Error when sending packet to satellite ({:?})", repno, e)

16
artiq/firmware/satman/routing.rs
View File

@ -1,5 +1,6 @@
use alloc::{vec::Vec, collections::vec_deque::VecDeque}; use alloc::{vec::Vec, collections::vec_deque::VecDeque};
use board_artiq::{drtioaux, drtio_routing}; use board_artiq::{drtioaux, drtio_routing};
#[cfg(has_drtio_routing)]
use board_misoc::csr; use board_misoc::csr;
use core::cmp::min; use core::cmp::min;
use proto_artiq::drtioaux_proto::PayloadStatus; use proto_artiq::drtioaux_proto::PayloadStatus;
@ -72,6 +73,7 @@ impl Sliceable {
pub struct Router { pub struct Router {
upstream_queue: VecDeque<drtioaux::Packet>, upstream_queue: VecDeque<drtioaux::Packet>,
local_queue: VecDeque<drtioaux::Packet>, local_queue: VecDeque<drtioaux::Packet>,
#[cfg(has_drtio_routing)]
downstream_queue: VecDeque<(usize, drtioaux::Packet)>, downstream_queue: VecDeque<(usize, drtioaux::Packet)>,
upstream_notified: bool, upstream_notified: bool,
} }
@ -81,6 +83,7 @@ impl Router {
Router { Router {
upstream_queue: VecDeque::new(), upstream_queue: VecDeque::new(),
local_queue: VecDeque::new(), local_queue: VecDeque::new(),
#[cfg(has_drtio_routing)]
downstream_queue: VecDeque::new(), downstream_queue: VecDeque::new(),
upstream_notified: false, upstream_notified: false,
} }
@ -90,14 +93,14 @@ impl Router {
// messages are always buffered for both upstream and downstream // messages are always buffered for both upstream and downstream
pub fn route(&mut self, packet: drtioaux::Packet, pub fn route(&mut self, packet: drtioaux::Packet,
_routing_table: &drtio_routing::RoutingTable, _rank: u8, _routing_table: &drtio_routing::RoutingTable, _rank: u8,
_self_destination: u8 self_destination: u8
) { ) {
let destination = packet.routable_destination();
#[cfg(has_drtio_routing)] #[cfg(has_drtio_routing)]
{ {
let destination = packet.routable_destination();
if let Some(destination) = destination { if let Some(destination) = destination {
let hop = _routing_table.0[destination as usize][_rank as usize] as usize; let hop = _routing_table.0[destination as usize][_rank as usize] as usize;
if destination == _self_destination { if destination == self_destination {
self.local_queue.push_back(packet); self.local_queue.push_back(packet);
} else if hop > 0 && hop < csr::DRTIOREP.len() { } else if hop > 0 && hop < csr::DRTIOREP.len() {
let repno = (hop - 1) as usize; let repno = (hop - 1) as usize;
@ -111,7 +114,11 @@ impl Router {
} }
#[cfg(not(has_drtio_routing))] #[cfg(not(has_drtio_routing))]
{ {
self.upstream_queue.push_back(packet); if destination == Some(self_destination) {
self.local_queue.push_back(packet);
} else {
self.upstream_queue.push_back(packet);
}
} }
} }
@ -166,6 +173,7 @@ impl Router {
packet packet
} }
#[cfg(has_drtio_routing)]
pub fn get_downstream_packet(&mut self) -> Option<(usize, drtioaux::Packet)> { pub fn get_downstream_packet(&mut self) -> Option<(usize, drtioaux::Packet)> {
self.downstream_queue.pop_front() self.downstream_queue.pop_front()
} }