From 6aa68e171590f908fc2ff010dd55fd3399955620 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Fri, 4 Oct 2019 22:56:16 +0800 Subject: [PATCH] sayma_rtm2: select filtered clock from Si5324 --- artiq/gateware/targets/sayma_rtm_drtio.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/artiq/gateware/targets/sayma_rtm_drtio.py b/artiq/gateware/targets/sayma_rtm_drtio.py index d6247652d..08d0589f3 100755 --- a/artiq/gateware/targets/sayma_rtm_drtio.py +++ b/artiq/gateware/targets/sayma_rtm_drtio.py @@ -136,6 +136,8 @@ class _SatelliteBase(BaseSoC): self.add_memory_group("drtioaux_mem", ["drtioaux0_mem"]) self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6) + if self.hw_rev == "v2.0": + self.comb += platform.request("filtered_clk_sel").eq(1) self.submodules.siphaser = SiPhaser7Series( si5324_clkin=platform.request("si5324_clkin"), rx_synchronizer=self.rx_synchronizer,