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grabber: use BUFR/BUFIO 

Less jitter and frees up BUFGs.
This commit is contained in:
Sebastien Bourdeauducq 2018-07-10 13:30:38 +08:00
parent 208dc7c218
commit 6a77032fa5
1 changed files with 4 additions and 10 deletions
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14
artiq/gateware/grabber/deserializer_7series.py
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@ -78,9 +78,7 @@ class Deserializer(Module, AutoCSR):
mmcm_fb = Signal() mmcm_fb = Signal()
mmcm_locked = Signal() mmcm_locked = Signal()
mmcm_ps_psdone = Signal() mmcm_ps_psdone = Signal()
cl_clk = Signal()
cl7x_clk = Signal() cl7x_clk = Signal()
phase = 257.0
self.specials += [ self.specials += [
Instance("MMCME2_ADV", Instance("MMCME2_ADV",
p_CLKIN1_PERIOD=18.0, p_CLKIN1_PERIOD=18.0,
@ -94,14 +92,9 @@ class Deserializer(Module, AutoCSR):
o_CLKFBOUT=mmcm_fb, i_CLKFBIN=mmcm_fb, o_CLKFBOUT=mmcm_fb, i_CLKFBIN=mmcm_fb,
p_CLKOUT0_USE_FINE_PS="TRUE",
p_CLKOUT0_DIVIDE_F=21.0,
p_CLKOUT0_PHASE=phase,
o_CLKOUT0=cl_clk,
p_CLKOUT1_USE_FINE_PS="TRUE", p_CLKOUT1_USE_FINE_PS="TRUE",
p_CLKOUT1_DIVIDE=3, p_CLKOUT1_DIVIDE=3,
p_CLKOUT1_PHASE=phase*7 % 360.0, p_CLKOUT1_PHASE=0.0,
o_CLKOUT1=cl7x_clk, o_CLKOUT1=cl7x_clk,
i_PSCLK=ClockSignal(), i_PSCLK=ClockSignal(),
@ -109,8 +102,9 @@ class Deserializer(Module, AutoCSR):
i_PSINCDEC=self.phase_shift.r, i_PSINCDEC=self.phase_shift.r,
o_PSDONE=mmcm_ps_psdone, o_PSDONE=mmcm_ps_psdone,
), ),
Instance("BUFG", i_I=cl_clk, o_O=self.cd_cl.clk), Instance("BUFR", p_BUFR_DIVIDE="7", i_CLR=~mmcm_locked,
Instance("BUFG", i_I=cl7x_clk, o_O=self.cd_cl7x.clk), i_I=cl7x_clk, o_O=self.cd_cl.clk),
Instance("BUFIO", i_I=cl7x_clk, o_O=self.cd_cl7x.clk),
AsyncResetSynchronizer(self.cd_cl, ~mmcm_locked), AsyncResetSynchronizer(self.cd_cl, ~mmcm_locked),
] ]
self.sync += [ self.sync += [