From 6a77032fa535c90eb4674d6a20304744f7173a88 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Tue, 10 Jul 2018 13:30:38 +0800 Subject: [PATCH] grabber: use BUFR/BUFIO Less jitter and frees up BUFGs. --- artiq/gateware/grabber/deserializer_7series.py | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-) diff --git a/artiq/gateware/grabber/deserializer_7series.py b/artiq/gateware/grabber/deserializer_7series.py index b7336a578..0224127fe 100644 --- a/artiq/gateware/grabber/deserializer_7series.py +++ b/artiq/gateware/grabber/deserializer_7series.py @@ -78,9 +78,7 @@ class Deserializer(Module, AutoCSR): mmcm_fb = Signal() mmcm_locked = Signal() mmcm_ps_psdone = Signal() - cl_clk = Signal() cl7x_clk = Signal() - phase = 257.0 self.specials += [ Instance("MMCME2_ADV", p_CLKIN1_PERIOD=18.0, @@ -94,14 +92,9 @@ class Deserializer(Module, AutoCSR): o_CLKFBOUT=mmcm_fb, i_CLKFBIN=mmcm_fb, - p_CLKOUT0_USE_FINE_PS="TRUE", - p_CLKOUT0_DIVIDE_F=21.0, - p_CLKOUT0_PHASE=phase, - o_CLKOUT0=cl_clk, - p_CLKOUT1_USE_FINE_PS="TRUE", p_CLKOUT1_DIVIDE=3, - p_CLKOUT1_PHASE=phase*7 % 360.0, + p_CLKOUT1_PHASE=0.0, o_CLKOUT1=cl7x_clk, i_PSCLK=ClockSignal(), @@ -109,8 +102,9 @@ class Deserializer(Module, AutoCSR): i_PSINCDEC=self.phase_shift.r, o_PSDONE=mmcm_ps_psdone, ), - Instance("BUFG", i_I=cl_clk, o_O=self.cd_cl.clk), - Instance("BUFG", i_I=cl7x_clk, o_O=self.cd_cl7x.clk), + Instance("BUFR", p_BUFR_DIVIDE="7", i_CLR=~mmcm_locked, + i_I=cl7x_clk, o_O=self.cd_cl.clk), + Instance("BUFIO", i_I=cl7x_clk, o_O=self.cd_cl7x.clk), AsyncResetSynchronizer(self.cd_cl, ~mmcm_locked), ] self.sync += [