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serwb: support single-ended signals 

Low-speed PHY only.
This commit is contained in:
Sebastien Bourdeauducq 2018-06-13 21:28:15 +08:00
parent f8627952c8
commit 68d16fc292
2 changed files with 19 additions and 5 deletions
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14
artiq/gateware/serwb/genphy.py
View File

@ -18,10 +18,18 @@ class _SerdesClocking(Module):
# can use this clock to sample data # can use this clock to sample data
if mode == "master": if mode == "master":
self.specials += DDROutput(0, 1, self.refclk) self.specials += DDROutput(0, 1, self.refclk)
if hasattr(pads, "clk_p"):
self.specials += DifferentialOutput(self.refclk, pads.clk_p, pads.clk_n) self.specials += DifferentialOutput(self.refclk, pads.clk_p, pads.clk_n)
else:
self.comb += pads.clk.eq(self.refclk)
# In Slave mode, use the clock provided by Master # In Slave mode, use the clock provided by Master
elif mode == "slave": elif mode == "slave":
if hasattr(pads, "clk_p"):
self.specials += DifferentialInput(pads.clk_p, pads.clk_n, self.refclk) self.specials += DifferentialInput(pads.clk_p, pads.clk_n, self.refclk)
else:
self.comb += self.refclk.eq(pads.clk)
else:
raise ValueError
class _SerdesTX(Module): class _SerdesTX(Module):
@ -47,7 +55,10 @@ class _SerdesTX(Module):
# Output data (on rising edge of sys_clk) # Output data (on rising edge of sys_clk)
data = Signal() data = Signal()
self.sync += data.eq(datapath.source.data) self.sync += data.eq(datapath.source.data)
if hasattr(pads, "tx_p"):
self.specials += DifferentialOutput(data, pads.tx_p, pads.tx_n) self.specials += DifferentialOutput(data, pads.tx_p, pads.tx_n)
else:
self.comb += pads.tx.eq(data)
class _SerdesRX(Module): class _SerdesRX(Module):
@ -67,7 +78,10 @@ class _SerdesRX(Module):
# Input data (on rising edge of sys_clk) # Input data (on rising edge of sys_clk)
data = Signal() data = Signal()
data_d = Signal() data_d = Signal()
if hasattr(pads, "rx_p"):
self.specials += DifferentialInput(pads.rx_p, pads.rx_n, data) self.specials += DifferentialInput(pads.rx_p, pads.rx_n, data)
else:
self.comb += data.eq(pads.rx)
self.sync += data_d.eq(data) self.sync += data_d.eq(data)
# Datapath # Datapath

2
artiq/gateware/targets/sayma_rtm.py
View File

@ -183,7 +183,7 @@ class SaymaRTM(Module):
# AMC/RTM serwb # AMC/RTM serwb
serwb_pads = platform.request("amc_rtm_serwb") serwb_pads = platform.request("amc_rtm_serwb")
platform.add_period_constraint(serwb_pads.clk_p, 8.) platform.add_period_constraint(serwb_pads.clk, 8.)
serwb_phy_rtm = serwb.genphy.SERWBPHY(platform.device, serwb_pads, mode="slave") serwb_phy_rtm = serwb.genphy.SERWBPHY(platform.device, serwb_pads, mode="slave")
self.submodules.serwb_phy_rtm = serwb_phy_rtm self.submodules.serwb_phy_rtm = serwb_phy_rtm
self.comb += [ self.comb += [