forked from M-Labs/artiq
remote coremgmt: restart device gracefully after flashing
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parent
b563533bc8
commit
67a2c63d2d
@ -143,6 +143,7 @@ pub enum Packet {
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CoreMgmtConfigReadReply { last: bool, length: u16, value: [u8; SAT_PAYLOAD_MAX_SIZE] },
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CoreMgmtAck,
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CoreMgmtNack,
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CoreMgmtRebootImminent,
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}
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impl Packet {
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@ -503,6 +504,7 @@ impl Packet {
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},
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0xdd => Packet::CoreMgmtAck,
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0xde => Packet::CoreMgmtNack,
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0xdf => Packet::CoreMgmtRebootImminent,
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ty => return Err(Error::UnknownPacket(ty))
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})
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@ -871,6 +873,7 @@ impl Packet {
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},
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Packet::CoreMgmtAck => writer.write_u8(0xdd)?,
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Packet::CoreMgmtNack => writer.write_u8(0xde)?,
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Packet::CoreMgmtRebootImminent => writer.write_u8(0xdf)?,
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}
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Ok(())
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}
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@ -352,6 +352,7 @@ mod remote_coremgmt {
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destination: destination, length: len as u16, last: status.is_last(), data: *slice});
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match reply {
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Ok(Packet::CoreMgmtAck) => Ok(()),
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Ok(Packet::CoreMgmtRebootImminent) if status.is_last() => Ok(()),
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Ok(packet) => {
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error!("received unexpected aux packet: {:?}", packet);
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Err(drtio::Error::UnexpectedReply)
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@ -556,17 +556,10 @@ fn process_aux_packet(dmamgr: &mut DmaManager, analyzer: &mut Analyzer, kernelmg
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forward!(router, _routing_table, _destination, *rank, *self_destination, _repeaters, &packet);
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coremgr.add_data(&data, length as usize);
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let mut succeeded = true;
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if last {
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succeeded = coremgr.write_config().is_ok();
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debug!("Write succeeded: {}", succeeded);
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coremgr.clear_data();
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}
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if succeeded {
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drtioaux::send(0, &drtioaux::Packet::CoreMgmtAck)
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coremgr.write_config()
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} else {
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drtioaux::send(0, &drtioaux::Packet::CoreMgmtNack)
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drtioaux::send(0, &drtioaux::Packet::CoreMgmtAck)
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}
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}
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drtioaux::Packet::CoreMgmtConfigRemoveRequest { destination: _destination, length, key } => {
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@ -1,13 +1,12 @@
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use alloc::vec::Vec;
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use routing::{Sliceable, SliceMeta};
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use board_misoc::config;
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use board_artiq::drtioaux;
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use board_misoc::{clock, config, csr, spiflash};
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use io::{Cursor, ProtoRead, ProtoWrite};
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use proto_artiq::drtioaux_proto::SAT_PAYLOAD_MAX_SIZE;
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type Result<T> = core::result::Result<T, ()>;
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pub struct Manager {
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current_payload: Cursor<Vec<u8>>,
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last_value: Sliceable,
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@ -21,7 +20,7 @@ impl Manager {
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}
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}
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pub fn fetch_config_value(&mut self, key: &str) -> Result<()> {
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pub fn fetch_config_value(&mut self, key: &str) -> Result<(), ()> {
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config::read(key, |result| result.map(
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|value| self.last_value = Sliceable::new(0, value.to_vec())
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)).map_err(|_err| warn!("read error: no such key"))
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@ -40,13 +39,44 @@ impl Manager {
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self.current_payload.set_position(0);
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}
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pub fn write_config(&mut self) -> Result<()> {
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let key = self.current_payload.read_string().map_err(
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|err| error!("error on reading key: {:?}", err))?;
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pub fn write_config(&mut self) -> Result<(), drtioaux::Error<!>> {
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let key = match self.current_payload.read_string() {
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Ok(key) => key,
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Err(err) => {
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self.clear_data();
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error!("error on reading key: {:?}", err);
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return drtioaux::send(0, &drtioaux::Packet::CoreMgmtNack);
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}
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};
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let value = self.current_payload.read_bytes().unwrap();
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config::write(&key, &value).map_err(|err| {
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error!("error on writing config: {:?}", err);
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})
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match key.as_str() {
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"gateware" | "bootloader" | "firmware" => {
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drtioaux::send(0, &drtioaux::Packet::CoreMgmtRebootImminent)?;
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#[cfg(not(soc_platform = "efc"))]
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unsafe {
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clock::spin_us(10000);
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csr::gt_drtio::txenable_write(0);
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}
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config::write(&key, &value).expect("failed to write to flash storage");
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warn!("restarting");
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unsafe { spiflash::reload(); }
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}
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_ => {
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let succeeded = config::write(&key, &value).map_err(|err| {
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error!("error on writing config: {:?}", err);
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}).is_ok();
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self.clear_data();
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if succeeded {
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drtioaux::send(0, &drtioaux::Packet::CoreMgmtAck)
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} else {
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drtioaux::send(0, &drtioaux::Packet::CoreMgmtNack)
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}
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}
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}
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}
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}
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