occheung
/
artiq
forked from M-Labs/artiq
1
0
Fork 0
Code Pull Requests Activity

spi: register clk

This commit is contained in:
Robert Jördens 2017-12-29 01:40:31 +08:00 committed by Sebastien Bourdeauducq
parent e6306b712d
commit 66d1647efd
1 changed files with 5 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
artiq/gateware/spi.py
View File

@ -208,9 +208,11 @@ class SPIMaster(Module):
clk_t = TSTriple() clk_t = TSTriple()
self.specials += clk_t.get_tristate(pads.clk) self.specials += clk_t.get_tristate(pads.clk)
self.comb += [ self.comb += clk_t.oe.eq(~config.offline),
clk_t.oe.eq(~config.offline), self.sync += [
clk_t.o.eq((spi.cg.clk & spi.cs) ^ config.clk_polarity), If(spi.cg.ce & spi.cg.edge,
clk_t.o.eq((~spi.cg.clk & spi.cs_next) ^ config.clk_polarity)
)
] ]
mosi_t = TSTriple() mosi_t = TSTriple()