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rtio: clean up error-prone rtlink.get_or_zero()

This commit is contained in:
Sebastien Bourdeauducq 2017-09-17 16:11:36 +08:00
parent 53860868f4
commit 65baca8c57
4 changed files with 16 additions and 15 deletions
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6
artiq/gateware/rtio/core.py
View File

@ -190,8 +190,10 @@ class Core(Module, AutoCSR):
self.specials += AsyncResetSynchronizer(self.cd_rio_phy, cmd_reset_phy) self.specials += AsyncResetSynchronizer(self.cd_rio_phy, cmd_reset_phy)
# TSC # TSC
fine_ts_width = max(rtlink.get_fine_ts_width(channel.interface) fine_ts_width = max(max(rtlink.get_fine_ts_width(channel.interface.o)
for channel in channels) for channel in channels),
max(rtlink.get_fine_ts_width(channel.interface.i)
for channel in channels))
coarse_ts = Signal(64-fine_ts_width) coarse_ts = Signal(64-fine_ts_width)
self.sync.rtio += coarse_ts.eq(coarse_ts + 1) self.sync.rtio += coarse_ts.eq(coarse_ts + 1)
coarse_ts_cdc = GrayCodeTransfer(len(coarse_ts)) coarse_ts_cdc = GrayCodeTransfer(len(coarse_ts))

7
artiq/gateware/rtio/rtlink.py
View File

@ -69,10 +69,9 @@ class Interface:
def _get_or_zero(interface, attr): def _get_or_zero(interface, attr):
if isinstance(interface, Interface): if interface is None:
return max(_get_or_zero(interface.i, attr), return 0
_get_or_zero(interface.o, attr)) assert isinstance(interface, (OInterface, IInterface))
else:
if hasattr(interface, attr): if hasattr(interface, attr):
return len(getattr(interface, attr)) return len(getattr(interface, attr))
else: else:

2
artiq/gateware/rtio/sed/core.py
View File

@ -27,7 +27,7 @@ class SED(Module):
else: else:
raise ValueError raise ValueError
fine_ts_width = max(rtlink.get_fine_ts_width(c.interface) fine_ts_width = max(rtlink.get_fine_ts_width(c.interface.o)
for c in channels) for c in channels)
seqn_width = layouts.seqn_width(lane_count, fifo_depth) seqn_width = layouts.seqn_width(lane_count, fifo_depth)

10
artiq/gateware/rtio/sed/layouts.py
View File

@ -4,9 +4,9 @@ from artiq.gateware.rtio import rtlink
def fifo_payload(channels): def fifo_payload(channels):
address_width = max(rtlink.get_address_width(channel.interface) address_width = max(rtlink.get_address_width(channel.interface.o)
for channel in channels) for channel in channels)
data_width = max(rtlink.get_data_width(channel.interface) data_width = max(rtlink.get_data_width(channel.interface.o)
for channel in channels) for channel in channels)
layout = [ layout = [
@ -46,11 +46,11 @@ def fifo_egress(seqn_width, layout_payload):
def output_network_payload(channels): def output_network_payload(channels):
fine_ts_width = max(rtlink.get_fine_ts_width(channel.interface) fine_ts_width = max(rtlink.get_fine_ts_width(channel.interface.o)
for channel in channels) for channel in channels)
address_width = max(rtlink.get_address_width(channel.interface) address_width = max(rtlink.get_address_width(channel.interface.o)
for channel in channels) for channel in channels)
data_width = max(rtlink.get_data_width(channel.interface) data_width = max(rtlink.get_data_width(channel.interface.o)
for channel in channels) for channel in channels)
layout = [("channel", bits_for(len(channels)-1))] layout = [("channel", bits_for(len(channels)-1))]