From 64c8eee28d6eec7db071842c8a67d21880998142 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 30 Apr 2018 23:59:56 +0200
Subject: [PATCH] serwb/phy/master: fix slave ready detection by filtering
 possible glitches on rx data (seems to happen when RTM fpga is not loaded)

---
 artiq/gateware/serwb/phy.py | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/artiq/gateware/serwb/phy.py b/artiq/gateware/serwb/phy.py
index fe6885ab9..8a921dbe6 100644
--- a/artiq/gateware/serwb/phy.py
+++ b/artiq/gateware/serwb/phy.py
@@ -58,7 +58,10 @@ class _SerdesMasterInit(Module):
         )
         fsm.act("SEND_PATTERN",
             If(~serdes.rx_idle,
-                NextState("WAIT_STABLE")
+                timer.wait.eq(1),
+                If(timer.done,
+                    NextState("CHECK_PATTERN")
+                )
             ),
             serdes.tx_comma.eq(1)
         )