diff --git a/RELEASE_NOTES.rst b/RELEASE_NOTES.rst
index 4ab9f0537..8b17bac8c 100644
--- a/RELEASE_NOTES.rst
+++ b/RELEASE_NOTES.rst
@@ -28,6 +28,7 @@ Highlights:
    - SERDES TTL inputs can now detect edges on pulses that are shorter
      than the RTIO period (https://github.com/m-labs/artiq/issues/1432)
    - Improved performance for kernel RPC involving list and array.
+   - Improved performance for computation involving loops.
 * Coredevice SI to mu conversions now always return valid codes, or raise a ``ValueError``.
 * Zotino now exposes  ``voltage_to_mu()``
 * ``ad9910``: The maximum amplitude scale factor is now ``0x3fff`` (was ``0x3ffe``
diff --git a/artiq/compiler/targets.py b/artiq/compiler/targets.py
index 9ebc7907d..8a9be0efc 100644
--- a/artiq/compiler/targets.py
+++ b/artiq/compiler/targets.py
@@ -105,7 +105,11 @@ class Target:
         return llmachine
 
     def optimize(self, llmodule):
+        pmb = llvm.create_pass_manager_builder()
+        pmb.slp_vectorize = True
+        pmb.loop_vectorize = True
         llpassmgr = llvm.create_module_pass_manager()
+        pmb.populate(llpassmgr)
 
         # Register our alias analysis passes.
         llpassmgr.add_basic_alias_analysis_pass()