occheung
/
artiq
forked from M-Labs/artiq
1
0
Fork 0
Code Pull Requests Activity

gtp_7series: simplify TX clocking

This commit is contained in:
Sebastien Bourdeauducq 2018-01-23 09:49:23 +08:00
parent 472840f16b
commit 626075cbc1
1 changed files with 1 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
artiq/gateware/drtio/transceiver/gtp_7series.py
View File

@ -175,16 +175,7 @@ class GTPSingle(Module):
self.sync += tx_reset_deglitched.eq(~tx_init.done)
self.clock_domains.cd_rtio_tx = ClockDomain()
if mode == "master":
txoutclk_bufg = Signal()
txoutclk_bufr = Signal()
tx_bufr_div = 150.e6/rtio_clk_freq
assert tx_bufr_div == int(tx_bufr_div)
self.specials += [
Instance("BUFG", i_I=self.txoutclk, o_O=txoutclk_bufg),
Instance("BUFR", i_I=txoutclk_bufg, o_O=txoutclk_bufr,
i_CE=1, p_BUFR_DIVIDE=str(int(tx_bufr_div))),
Instance("BUFG", i_I=txoutclk_bufr, o_O=self.cd_rtio_tx.clk)
]
self.specials += Instance("BUFG", i_I=self.txoutclk, o_O=self.cd_rtio_tx.clk)
self.specials += AsyncResetSynchronizer(self.cd_rtio_tx, tx_reset_deglitched)
# rx clocking