forked from M-Labs/artiq
rtio/sed: add unittest for sequence number rollover
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@ -10,7 +10,7 @@ from artiq.gateware.rtio.phy import ttl_simple
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class DUT(Module):
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class DUT(Module):
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def __init__(self):
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def __init__(self, **kwargs):
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self.ttl0 = Signal()
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self.ttl0 = Signal()
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self.ttl1 = Signal()
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self.ttl1 = Signal()
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@ -22,15 +22,15 @@ class DUT(Module):
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rtio.Channel.from_phy(self.phy1)
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rtio.Channel.from_phy(self.phy1)
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]
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]
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self.submodules.sed = SED(rtio_channels, 0, "sync")
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self.submodules.sed = SED(rtio_channels, 0, "sync", **kwargs)
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self.sync += [
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self.sync += [
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self.sed.coarse_timestamp.eq(self.sed.coarse_timestamp + 1),
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self.sed.coarse_timestamp.eq(self.sed.coarse_timestamp + 1),
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self.sed.minimum_coarse_timestamp.eq(self.sed.coarse_timestamp + 16)
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self.sed.minimum_coarse_timestamp.eq(self.sed.coarse_timestamp + 16)
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]
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]
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def simulate(input_events):
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def simulate(input_events, **kwargs):
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dut = DUT()
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dut = DUT(**kwargs)
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ttl_changes = []
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ttl_changes = []
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access_results = []
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access_results = []
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@ -97,5 +97,19 @@ class TestSED(unittest.TestCase):
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input_events += [(now, 1), (now, 0)]
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input_events += [(now, 1), (now, 0)]
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ttl_changes, access_results = simulate(input_events)
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ttl_changes, access_results = simulate(input_events)
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self.assertEqual(ttl_changes, list(range(40, 140, 10)))
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self.assertEqual(access_results, [("ok", 0)]*len(input_events))
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self.assertEqual(access_results, [("ok", 0)]*len(input_events))
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self.assertEqual(ttl_changes, list(range(40, 40+5*20, 10)))
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def test_replace_rollover(self):
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input_events = []
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now = 24
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for i in range(40):
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now += 10
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input_events += [(now, 1)]
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now += 10
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input_events += [(now, 1), (now, 0)]
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ttl_changes, access_results = simulate(input_events,
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lane_count=2, fifo_depth=2, enable_spread=False)
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self.assertEqual([r[0] for r in access_results], ["ok"]*len(input_events))
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self.assertEqual(ttl_changes, list(range(40, 40+40*20, 10)))
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