forked from M-Labs/artiq
Fully drop AD9858 and kc705-nist_qc1 support (closes #576).
This commit is contained in:
whitequark
parent
f4b7666768
commit
5e8888d5f3
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@ -52,43 +52,3 @@ papilio_adapter_io = [
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Subsignal("rst_n", Pins("A:3")),
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IOStandard("LVTTL")),
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]
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fmc_adapter_io = [
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("pmt", 0, Pins("LPC:LA20_N"), IOStandard("LVTTL")),
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("pmt", 1, Pins("LPC:LA24_P"), IOStandard("LVTTL")),
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("ttl", 0, Pins("LPC:LA21_P"), IOStandard("LVTTL")),
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("ttl", 1, Pins("LPC:LA25_P"), IOStandard("LVTTL")),
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("ttl", 2, Pins("LPC:LA21_N"), IOStandard("LVTTL")),
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("ttl", 3, Pins("LPC:LA25_N"), IOStandard("LVTTL")),
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("ttl", 4, Pins("LPC:LA22_P"), IOStandard("LVTTL")),
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("ttl", 5, Pins("LPC:LA26_P"), IOStandard("LVTTL")),
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("ttl", 6, Pins("LPC:LA22_N"), IOStandard("LVTTL")),
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("ttl", 7, Pins("LPC:LA26_N"), IOStandard("LVTTL")),
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("ttl", 8, Pins("LPC:LA23_P"), IOStandard("LVTTL")),
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("ttl", 9, Pins("LPC:LA27_P"), IOStandard("LVTTL")),
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("ttl", 10, Pins("LPC:LA23_N"), IOStandard("LVTTL")),
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("ttl", 11, Pins("LPC:LA27_N"), IOStandard("LVTTL")),
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("ttl", 12, Pins("LPC:LA00_CC_P"), IOStandard("LVTTL")),
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("ttl", 13, Pins("LPC:LA10_P"), IOStandard("LVTTL")),
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("ttl", 14, Pins("LPC:LA00_CC_N"), IOStandard("LVTTL")),
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("ttl", 15, Pins("LPC:LA10_N"), IOStandard("LVTTL")),
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("ttl_l_tx_en", 0, Pins("LPC:LA11_P"), IOStandard("LVTTL")),
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("ttl_h_tx_en", 0, Pins("LPC:LA01_CC_P"), IOStandard("LVTTL")),
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("dds", 0,
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Subsignal("a", Pins("LPC:LA04_N LPC:LA14_N LPC:LA05_P LPC:LA15_P "
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"LPC:LA05_N LPC:LA15_N")),
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Subsignal("d", Pins("LPC:LA06_P LPC:LA16_P LPC:LA06_N LPC:LA16_N "
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"LPC:LA07_P LPC:LA17_CC_P LPC:LA07_N "
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"LPC:LA17_CC_N")),
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Subsignal("sel", Pins("LPC:LA12_N LPC:LA03_P LPC:LA13_P LPC:LA03_N "
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"LPC:LA13_N")),
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Subsignal("p", Pins("LPC:LA11_N LPC:LA02_P")),
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Subsignal("fud_n", Pins("LPC:LA14_P")),
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Subsignal("wr_n", Pins("LPC:LA04_P")),
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Subsignal("rd_n", Pins("LPC:LA02_N")),
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Subsignal("rst_n", Pins("LPC:LA12_P")),
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IOStandard("LVTTL")),
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]
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@ -56,11 +56,6 @@ class _AD9xxx(Module):
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for c, (probe, ftw) in enumerate(zip(self.probes, ftws))])
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class AD9858(_AD9xxx):
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def __init__(self, *args, **kwargs):
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_AD9xxx.__init__(self, 0x0a, *args, **kwargs)
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class AD9914(_AD9xxx):
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def __init__(self, *args, **kwargs):
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_AD9xxx.__init__(self, 0x2d, *args, **kwargs)
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@ -17,7 +17,7 @@ from misoc.targets.kc705 import MiniSoC, soc_kc705_args, soc_kc705_argdict
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from misoc.integration.builder import builder_args, builder_argdict
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from artiq.gateware.soc import AMPSoC, build_artiq_soc
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from artiq.gateware import rtio, nist_qc1, nist_clock, nist_qc2
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from artiq.gateware import rtio, nist_clock, nist_qc2
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from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series, dds, spi
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from artiq import __version__ as artiq_version
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@ -158,62 +158,6 @@ class _NIST_Ions(MiniSoC, AMPSoC):
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self.csr_devices.append("rtio_analyzer")
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class NIST_QC1(_NIST_Ions):
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"""
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NIST QC1 hardware, as used in the Penning lab, with FMC to SCSI cables
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adapter.
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"""
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def __init__(self, cpu_type="or1k", **kwargs):
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_NIST_Ions.__init__(self, cpu_type, **kwargs)
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platform = self.platform
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platform.add_extension(nist_qc1.fmc_adapter_io)
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self.comb += [
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platform.request("ttl_l_tx_en").eq(1),
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platform.request("ttl_h_tx_en").eq(1)
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]
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rtio_channels = []
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for i in range(2):
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phy = ttl_serdes_7series.Inout_8X(platform.request("pmt", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
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for i in range(15):
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phy = ttl_serdes_7series.Output_8X(platform.request("ttl", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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phy = ttl_serdes_7series.Inout_8X(platform.request("user_sma_gpio_n_33"))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
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phy = ttl_simple.Output(platform.request("user_led", 2))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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self.config["RTIO_REGULAR_TTL_COUNT"] = len(rtio_channels)
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phy = ttl_simple.ClockGen(platform.request("ttl", 15))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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self.config["RTIO_FIRST_DDS_CHANNEL"] = len(rtio_channels)
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self.config["RTIO_DDS_COUNT"] = 1
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self.config["DDS_CHANNELS_PER_BUS"] = 8
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self.config["DDS_AD9858"] = None
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phy = dds.AD9858(platform.request("dds"), 8)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy,
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ofifo_depth=512,
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ififo_depth=4))
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self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
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rtio_channels.append(rtio.LogChannel())
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self.add_rtio(rtio_channels)
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assert self.rtio.fine_ts_width <= 3
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self.config["DDS_RTIO_CLK_RATIO"] = 8 >> self.rtio.fine_ts_width
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class NIST_CLOCK(_NIST_Ions):
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"""
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NIST clock hardware, with old backplane and 11 DDS channels
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@ -372,19 +316,17 @@ class NIST_QC2(_NIST_Ions):
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def main():
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parser = argparse.ArgumentParser(
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description="ARTIQ core device builder / KC705 "
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"+ NIST Ions QC1/CLOCK/QC2 hardware adapters")
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"+ NIST Ions CLOCK/QC2 hardware adapters")
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builder_args(parser)
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soc_kc705_args(parser)
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parser.add_argument("-H", "--hw-adapter", default="nist_clock",
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help="hardware adapter type: "
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"nist_qc1/nist_clock/nist_qc2 "
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"nist_clock/nist_qc2 "
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"(default: %(default)s)")
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args = parser.parse_args()
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hw_adapter = args.hw_adapter.lower()
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if hw_adapter == "nist_qc1":
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cls = NIST_QC1
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elif hw_adapter == "nist_clock":
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if hw_adapter == "nist_clock":
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cls = NIST_CLOCK
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elif hw_adapter == "nist_qc2":
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cls = NIST_QC2
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@ -206,19 +206,6 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
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rtio_channels.append(rtio.Channel.from_phy(
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phy, ofifo_depth=64, ififo_depth=64))
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self.config["HAS_DDS"] = None
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self.config["RTIO_FIRST_DDS_CHANNEL"] = len(rtio_channels)
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self.config["RTIO_DDS_COUNT"] = 1
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self.config["DDS_CHANNELS_PER_BUS"] = 8
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self.config["DDS_AD9858"] = None
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dds_pins = platform.request("dds")
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self.comb += dds_pins.p.eq(0)
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phy = dds.AD9858(dds_pins, 8)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy,
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ofifo_depth=128,
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ififo_depth=4))
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self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
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rtio_channels.append(rtio.LogChannel())
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@ -105,17 +105,6 @@ static mut API: &'static [(&'static str, *const ())] = &[
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api!(rtio_input_timestamp),
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api!(rtio_input_data),
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#[cfg(has_dds)]
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api!(dds_init),
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#[cfg(has_dds)]
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api!(dds_init_sync),
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#[cfg(has_dds)]
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api!(dds_batch_enter),
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#[cfg(has_dds)]
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api!(dds_batch_exit),
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#[cfg(has_dds)]
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api!(dds_set),
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api!(i2c_init),
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api!(i2c_start),
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api!(i2c_stop),
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@ -1,14 +0,0 @@
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#!/bin/bash
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BUILD_SETTINGS_FILE=$HOME/.m-labs/build_settings.sh
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[ -f $BUILD_SETTINGS_FILE ] && . $BUILD_SETTINGS_FILE
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SOC_PREFIX=$PREFIX/lib/python3.5/site-packages/artiq/binaries/kc705-nist_qc1
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mkdir -p $SOC_PREFIX
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$PYTHON -m artiq.gateware.targets.kc705 -H nist_qc1 --toolchain vivado $MISOC_EXTRA_VIVADO_CMDLINE
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cp misoc_nist_qc1_kc705/gateware/top.bit $SOC_PREFIX
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cp misoc_nist_qc1_kc705/software/bios/bios.bin $SOC_PREFIX
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cp misoc_nist_qc1_kc705/software/runtime/runtime.fbi $SOC_PREFIX
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wget -P $SOC_PREFIX https://raw.githubusercontent.com/jordens/bscan_spi_bitstreams/master/bscan_spi_xc7k325t.bit
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@ -1,27 +0,0 @@
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package:
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name: artiq-kc705-nist_qc1
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version: {{ environ.get("GIT_DESCRIBE_TAG", "") }}
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source:
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git_url: ../..
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build:
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noarch_python: true
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number: {{ environ.get("GIT_DESCRIBE_NUMBER", 0) }}
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string: py_{{ environ.get("GIT_DESCRIBE_NUMBER", 0) }}+git{{ environ.get("GIT_DESCRIBE_HASH", "")[1:] }}
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requirements:
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build:
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- migen 0.5.dev
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- misoc 0.5.dev
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- llvm-or1k
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- binutils-or1k-linux >=2.27
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- rust-core-or1k
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- cargo
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run:
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- artiq {{ "{tag} py_{number}+git{hash}".format(tag=environ.get("GIT_DESCRIBE_TAG"), number=environ.get("GIT_DESCRIBE_NUMBER"), hash=environ.get("GIT_DESCRIBE_HASH")[1:]) if "GIT_DESCRIBE_TAG" in environ else "" }}
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about:
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home: https://m-labs.hk/artiq
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license: GPL
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summary: 'Bitstream, BIOS and runtime for NIST_QC1 on the KC705 board'
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@ -29,13 +29,13 @@ All boards have a serial interface running at 115200bps 8-N-1 that can be used f
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KC705
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-----
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The main target board for the ARTIQ core device is the KC705 development board from Xilinx. It supports the NIST QC1 hardware via an adapter, and the NIST CLOCK and QC2 hardware (FMC).
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The main target board for the ARTIQ core device is the KC705 development board from Xilinx. It supports the NIST CLOCK and QC2 hardware (FMC).
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Common problems
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+++++++++++++++
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* The SW13 switches on the board need to be set to 00001.
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* When connected, QC1 and CLOCK adapters break the JTAG chain due to TDI not being connect to TDO on the FMC mezzanine.
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* When connected, CLOCK adapter breaks the JTAG chain due to TDI not being connect to TDO on the FMC mezzanine.
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* On some boards, the JTAG USB connector is not correctly soldered.
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VADJ
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@ -44,31 +44,6 @@ VADJ
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With the NIST CLOCK and QC2 adapters, for safe operation of the DDS buses (to prevent damage to the IO banks of the FPGA), the FMC VADJ rail of the KC705 should be changed to 3.3V. Plug the Texas Instruments USB-TO-GPIO PMBus adapter into the PMBus connector in the corner of the KC705 and use the Fusion Digital Power Designer software to configure (requires Windows). Write to chip number U55 (address 52), channel 4, which is the VADJ rail, to make it 3.3V instead of 2.5V. Power cycle the KC705 board to check that the startup voltage on the VADJ rail is now 3.3V.
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NIST QC1
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++++++++
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With the QC1 hardware, the TTL lines are mapped as follows:
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+--------------+------------+--------------+
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| RTIO channel | TTL line | Capability |
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+==============+============+==============+
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| 0 | PMT0 | Input |
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+--------------+------------+--------------+
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| 1 | PMT1 | Input |
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+--------------+------------+--------------+
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| 2-16 | TTL0-14 | Output |
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+--------------+------------+--------------+
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| 17 | SMA_GPIO_N | Input+Output |
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+--------------+------------+--------------+
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| 18 | LED | Output |
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+--------------+------------+--------------+
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| 19 | TTL15 | Clock |
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+--------------+------------+--------------+
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There are no SPI channels.
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The DDS bus is on channel 20.
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NIST CLOCK
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++++++++++
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@ -202,5 +177,3 @@ Interface Type 2 (SPI) and 2A (expanded SPI):
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+==============+========+========+========+========+
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| 23 | PMOD_0 | PMOD_1 | PMOD_2 | PMOD_3 |
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+--------------+--------+--------+--------+--------+
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The DDS bus is on channel 24.
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@ -43,8 +43,7 @@ Then prepare to create a new conda environment with the ARTIQ package and the ma
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choose a suitable name for the environment, for example ``artiq-main`` if you intend to track the main label or ``artiq-2016-04-01`` if you consider the environment a snapshot of ARTIQ on 2016-04-01.
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Choose the package containing the binaries for your hardware:
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* ``artiq-pipistrello-nist_qc1`` for the `Pipistrello <http://pipistrello.saanlima.com/>`_ board with the NIST adapter to SCSI cables and AD9858 DDS chips.
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* ``artiq-kc705-nist_qc1`` for the `KC705 <http://www.xilinx.com/products/boards-and-kits/ek-k7-kc705-g.html>`_ board with the NIST adapter to SCSI cables and AD9858 DDS chips.
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* ``artiq-pipistrello-nist_qc1`` for the `Pipistrello <http://pipistrello.saanlima.com/>`_ board with the NIST adapter to SCSI cables; AD9858 DDS chips are not supported anymore.
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* ``artiq-kc705-nist_clock`` for the KC705 board with the NIST "clock" FMC backplane and AD9914 DDS chips.
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* ``artiq-kc705-nist_qc2`` for the KC705 board with the NIST QC2 FMC backplane and AD9914 DDS chips.
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@ -136,7 +135,7 @@ Then, you can flash the board:
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* For the KC705 board (selecting the appropriate hardware peripheral)::
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$ artiq_flash -t kc705 -m [nist_qc1/nist_clock/nist_qc2]
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$ artiq_flash -t kc705 -m [nist_clock/nist_qc2]
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The SW13 switches also need to be set to 00001.
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@ -171,7 +171,7 @@ These steps are required to generate gateware bitstream (``.bit``) files, build
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* For KC705::
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$ python3.5 -m artiq.gateware.targets.kc705 -H nist_qc1 # or nist_qc2
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$ python3.5 -m artiq.gateware.targets.kc705 -H nist_clock # or nist_qc2
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.. note:: Add ``--toolchain ise`` if you wish to use ISE instead of Vivado.
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