From 5cfa8d9a42121cb050412388aed4468dd35bb888 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Robert=20J=C3=B6rdens?= Date: Fri, 23 Sep 2022 11:54:40 +0000 Subject: [PATCH] add tester support, refactor gateware mode --- artiq/coredevice/phaser.py | 17 +++++++----- artiq/frontend/artiq_ddb_template.py | 14 ++++++---- artiq/frontend/artiq_sinara_tester.py | 39 ++++++++++++++++++--------- 3 files changed, 45 insertions(+), 25 deletions(-) diff --git a/artiq/coredevice/phaser.py b/artiq/coredevice/phaser.py index 94012ad69..4afe0c992 100644 --- a/artiq/coredevice/phaser.py +++ b/artiq/coredevice/phaser.py @@ -9,6 +9,10 @@ from artiq.coredevice.trf372017 import TRF372017 PHASER_BOARD_ID = 19 + +PHASER_GW_BASE = 1 +PHASER_GW_MIQRO = 2 + PHASER_ADDR_BOARD_ID = 0x00 PHASER_ADDR_HW_REV = 0x01 PHASER_ADDR_GW_REV = 0x02 @@ -222,7 +226,7 @@ class Phaser: def __init__(self, dmgr, channel_base, miso_delay=1, tune_fifo_offset=True, clk_sel=0, sync_dly=0, dac=None, trf0=None, trf1=None, - mode="base", core_device="core"): + core_device="core"): self.channel_base = channel_base self.core = dmgr.get(core_device) # TODO: auto-align miso-delay in phy @@ -235,6 +239,7 @@ class Phaser: self.clk_sel = clk_sel self.tune_fifo_offset = tune_fifo_offset self.sync_dly = sync_dly + self.gw_rev = -1 # discovered in init() self.dac_mmap = DAC34H84(dac).get_mmap() @@ -258,12 +263,10 @@ class Phaser: delay(.1*ms) # slack is_baseband = hw_rev & PHASER_HW_REV_VARIANT - gw_rev = self.read8(PHASER_ADDR_GW_REV) + self.gw_rev = self.read8(PHASER_ADDR_GW_REV) if debug: - print("gw_rev:", gw_rev) + print("gw_rev:", self.gw_rev) self.core.break_realtime() - is_base = gw_rev == 1 - is_miqro = gw_rev == 2 delay(.1*ms) # slack # allow a few errors during startup and alignment since boot @@ -384,7 +387,7 @@ class Phaser: channel.set_servo(profile=0, enable=0, hold=1) - if is_base: + if self.gw_rev == PHASER_GW_BASE: # test oscillators and DUC for i in range(len(channel.oscillator)): oscillator = channel.oscillator[i] @@ -412,7 +415,7 @@ class Phaser: abs(data_i - data_q) > 2): raise ValueError("DUC+oscillator phase/amplitude test failed") - if is_miqro: + if self.gw_rev == PHASER_GW_MIQRO: channel.miqro.reset() if is_baseband: diff --git a/artiq/frontend/artiq_ddb_template.py b/artiq/frontend/artiq_ddb_template.py index 503f4862e..5459756fe 100755 --- a/artiq/frontend/artiq_ddb_template.py +++ b/artiq/frontend/artiq_ddb_template.py @@ -560,6 +560,12 @@ class PeripheralManager: def process_phaser(self, rtio_offset, peripheral): mode = peripheral.get("mode", "base") + if mode == "miqro": + dac = ', "dac": {"pll_m": 16, "pll_n": 3, "interpolation": 2}' + n_channels = 3 + else: + dac = "" + n_channels = 5 self.gen(""" device_db["{name}"] = {{ "type": "local", @@ -567,15 +573,13 @@ class PeripheralManager: "class": "Phaser", "arguments": {{ "channel_base": 0x{channel:06x}, - "miso_delay": 1, - "mode": "{mode}" + "miso_delay": 1{dac} }} }}""", name=self.get_name("phaser"), - mode=mode, + dac=dac, channel=rtio_offset) - rtio_channels = {"base": 5, "miqro": 3}[mode] - return rtio_channels + return n_channels def process_hvamp(self, rtio_offset, peripheral): hvamp_name = self.get_name("hvamp") diff --git a/artiq/frontend/artiq_sinara_tester.py b/artiq/frontend/artiq_sinara_tester.py index a4f999029..fea05bbcd 100755 --- a/artiq/frontend/artiq_sinara_tester.py +++ b/artiq/frontend/artiq_sinara_tester.py @@ -570,20 +570,33 @@ class SinaraTester(EnvExperiment): self.core.break_realtime() phaser.init() delay(1*ms) - phaser.channel[0].set_duc_frequency(duc) - phaser.channel[0].set_duc_cfg() - phaser.channel[0].set_att(6*dB) - phaser.channel[1].set_duc_frequency(-duc) - phaser.channel[1].set_duc_cfg() - phaser.channel[1].set_att(6*dB) - phaser.duc_stb() - delay(1*ms) - for i in range(len(osc)): - phaser.channel[0].oscillator[i].set_frequency(osc[i]) - phaser.channel[0].oscillator[i].set_amplitude_phase(.2) - phaser.channel[1].oscillator[i].set_frequency(-osc[i]) - phaser.channel[1].oscillator[i].set_amplitude_phase(.2) + if phaser.gw_rev == 1: # base + phaser.channel[0].set_duc_frequency(duc) + phaser.channel[0].set_duc_cfg() + phaser.channel[0].set_att(6*dB) + phaser.channel[1].set_duc_frequency(-duc) + phaser.channel[1].set_duc_cfg() + phaser.channel[1].set_att(6*dB) + phaser.duc_stb() delay(1*ms) + for i in range(len(osc)): + phaser.channel[0].oscillator[i].set_frequency(osc[i]) + phaser.channel[0].oscillator[i].set_amplitude_phase(.2) + phaser.channel[1].oscillator[i].set_frequency(-osc[i]) + phaser.channel[1].oscillator[i].set_amplitude_phase(.2) + delay(1*ms) + elif phaser.gw_rev == 2: # miqro + for ch in range(2): + delay(1*ms) + phaser.channel[ch].set_att(6*dB) + phaser.channel[ch].miqro.set_window( + start=0x00, iq=[[1., 0.]], order=0, tail=0) + sign = 1. - 2.*ch + for i in range(len(osc)): + phaser.channel[ch].miqro.set_profile(osc, profile=1, + frequency=sign*(duc + osc[i]), amplitude=1./len(osc)) + phaser.channel[ch].miqro.pulse( + window=0x000, profiles=[1 for _ in range(len(osc))]) @kernel def phaser_led_wave(self, phasers):