forked from M-Labs/artiq
remove phaser, adapt SAWG example to Sayma
This commit is contained in:
parent
5809e08686
commit
569484f888
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@ -1,13 +1,11 @@
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# The RTIO channel numbers here are for Phaser on KC705.
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core_addr = "kc705aux.lab.m-labs.hk"
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core_addr = "sayma1.lab.m-labs.hk"
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device_db = {
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"core": {
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"type": "local",
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"module": "artiq.coredevice.core",
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"class": "Core",
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"arguments": {"host": core_addr, "ref_period": 5e-9/6}
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"arguments": {"host": core_addr, "ref_period": 1/(150e6)}
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},
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"core_log": {
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"type": "controller",
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@ -20,57 +18,96 @@ device_db = {
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"module": "artiq.coredevice.cache",
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"class": "CoreCache"
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},
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"ttl_sma": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLInOut",
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"arguments": {"channel": 0}
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},
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"led": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 1}
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},
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"sysref": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLInOut",
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"arguments": {"channel": 2}
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},
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"converter_spi": {
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"type": "local",
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"module": "artiq.coredevice.spi",
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"class": "NRTSPIMaster",
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},
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"ad9154_spi": {
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"ad9154_spi0": {
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"type": "local",
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"module": "artiq.coredevice.ad9154_spi",
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"class": "AD9154",
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"arguments": {"spi_device": "converter_spi", "chip_select": 1}
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"arguments": {"spi_device": "converter_spi", "chip_select": 2}
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},
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"ad9154_spi1": {
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"type": "local",
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"module": "artiq.coredevice.ad9154_spi",
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"class": "AD9154",
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"arguments": {"spi_device": "converter_spi", "chip_select": 3}
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},
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"led0": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 0}
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},
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"led1": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 1}
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},
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"ttl_sma0": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 2}
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},
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"ttl_sma1": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 3}
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},
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"sawg0": {
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"type": "local",
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"module": "artiq.coredevice.sawg",
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"class": "SAWG",
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"arguments": {"channel_base": 3, "parallelism": 2}
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"arguments": {"channel_base": 4, "parallelism": 4}
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},
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"sawg1": {
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"type": "local",
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"module": "artiq.coredevice.sawg",
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"class": "SAWG",
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"arguments": {"channel_base": 13, "parallelism": 2}
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"arguments": {"channel_base": 14, "parallelism": 4}
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},
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"sawg2": {
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"type": "local",
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"module": "artiq.coredevice.sawg",
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"class": "SAWG",
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"arguments": {"channel_base": 23, "parallelism": 2}
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"arguments": {"channel_base": 24, "parallelism": 4}
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},
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"sawg3": {
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"type": "local",
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"module": "artiq.coredevice.sawg",
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"class": "SAWG",
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"arguments": {"channel_base": 33, "parallelism": 2}
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}
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"arguments": {"channel_base": 34, "parallelism": 4}
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},
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"sawg4": {
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"type": "local",
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"module": "artiq.coredevice.sawg",
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"class": "SAWG",
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"arguments": {"channel_base": 44, "parallelism": 4}
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},
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"sawg5": {
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"type": "local",
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"module": "artiq.coredevice.sawg",
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"class": "SAWG",
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"arguments": {"channel_base": 54, "parallelism": 4}
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},
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"sawg6": {
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"type": "local",
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"module": "artiq.coredevice.sawg",
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"class": "SAWG",
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"arguments": {"channel_base": 64, "parallelism": 4}
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},
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"sawg7": {
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"type": "local",
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"module": "artiq.coredevice.sawg",
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"class": "SAWG",
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"arguments": {"channel_base": 74, "parallelism": 4}
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},
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}
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@ -4,8 +4,7 @@ from artiq.experiment import *
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class SAWGTest(EnvExperiment):
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def build(self):
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self.setattr_device("core")
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self.setattr_device("led")
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self.setattr_device("ttl_sma")
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self.setattr_device("ttl_sma0")
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self.setattr_device("sawg0")
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self.setattr_device("sawg1")
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@ -15,7 +14,6 @@ class SAWGTest(EnvExperiment):
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@kernel
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def run(self):
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self.core.reset()
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self.ttl_sma.output()
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while True:
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self.sawg0.amplitude1.set(0.)
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@ -30,21 +28,21 @@ class SAWGTest(EnvExperiment):
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self.sawg1.amplitude1.set(.4)
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self.sawg1.frequency0.set(10*MHz)
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self.sawg1.phase0.set(0.)
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self.ttl_sma.pulse(200*ns)
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self.ttl_sma0.pulse(200*ns)
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self.sawg1.amplitude1.set(.1)
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delay(200*ns)
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self.sawg1.amplitude1.set(-.4)
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self.ttl_sma.pulse(200*ns)
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self.ttl_sma0.pulse(200*ns)
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self.sawg1.amplitude1.set(.4)
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delay(200*ns)
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self.sawg1.phase0.set(.25)
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self.ttl_sma.pulse(200*ns)
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self.ttl_sma0.pulse(200*ns)
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self.sawg1.phase0.set(.5)
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delay(200*ns)
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self.sawg0.phase0.set(.5)
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self.ttl_sma.pulse(200*ns)
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self.ttl_sma0.pulse(200*ns)
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self.sawg1.frequency0.set(30*MHz)
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delay(200*ns)
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self.sawg1.frequency0.set(10*MHz)
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self.sawg1.phase0.set(0.)
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self.ttl_sma.pulse(200*ns)
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self.ttl_sma0.pulse(200*ns)
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@ -4,8 +4,8 @@ from artiq.experiment import *
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class SAWGTestTwoTone(EnvExperiment):
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def build(self):
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self.setattr_device("core")
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self.setattr_device("led")
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self.setattr_device("ttl_sma")
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self.setattr_device("led0")
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self.setattr_device("ttl_sma0")
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self.setattr_device("sawg0")
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self.setattr_device("sawg1")
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@ -17,8 +17,6 @@ class SAWGTestTwoTone(EnvExperiment):
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self.core.reset()
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delay(1*ms)
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self.ttl_sma.output()
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self.sawg0.reset()
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self.sawg1.reset()
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self.sawg2.reset()
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@ -38,8 +36,8 @@ class SAWGTestTwoTone(EnvExperiment):
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order = 3
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delay(20*ms)
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self.led.on()
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self.ttl_sma.on()
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self.led0.on()
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self.ttl_sma0.on()
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self.sawg0.frequency0.set(10*MHz)
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self.sawg0.phase0.set(0.)
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self.sawg0.frequency1.set(1*MHz)
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@ -60,5 +58,5 @@ class SAWGTestTwoTone(EnvExperiment):
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self.sawg1.amplitude1.set(.0)
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self.sawg1.amplitude2.set(.0)
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self.ttl_sma.off()
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self.led.off()
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self.ttl_sma0.off()
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self.led0.off()
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@ -5,7 +5,7 @@ from artiq.experiment import *
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class Test(EnvExperiment):
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def build(self):
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self.setattr_device("core")
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self.setattr_device("ad9154_spi")
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self.ad9154_spi = self.get_device("ad9154_spi0")
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@kernel
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def run(self):
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@ -1,74 +0,0 @@
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from migen.build.generic_platform import *
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ad9154_fmc_ebz = [
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("ad9154_spi", 0,
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# AD9154 should give control of SPI to FMC when USB cable is unplugged,
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# It's the case, but the PIC18F24J50 is introducing noise on SPI SCK
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# (???) To workaround that, add 2 jumpers:
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# - on XP1, between pin 5 and 6 (will keep the PIC in reset)
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# - on JP3 (will force output enable on FXLA108)
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Subsignal("clk", Pins("HPC:LA03_P")),
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Subsignal("cs_n", Pins("HPC:LA04_N", "HPC:LA05_P")),
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Subsignal("mosi", Pins("HPC:LA03_N")),
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Subsignal("miso", Pins("HPC:LA04_P")),
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Subsignal("en", Pins("HPC:LA05_N")),
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IOStandard("LVCMOS25"),
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),
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("ad9154_txen", 0, Pins("HPC:LA07_P"), IOStandard("LVCMOS25")),
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("ad9154_txen", 1, Pins("HPC:LA07_N"), IOStandard("LVCMOS25")),
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("ad9154_refclk", 0,
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Subsignal("p", Pins("HPC:GBTCLK0_M2C_P")),
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Subsignal("n", Pins("HPC:GBTCLK0_M2C_N")),
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),
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("ad9154_sysref", 0,
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Subsignal("p", Pins("HPC:LA00_CC_P")),
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Subsignal("n", Pins("HPC:LA00_CC_N")),
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IOStandard("LVDS_25"),
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Misc("DIFF_TERM=TRUE"),
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),
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("ad9154_sync", 0,
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Subsignal("p", Pins("HPC:LA01_CC_P")),
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Subsignal("n", Pins("HPC:LA01_CC_N")),
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IOStandard("LVDS_25"),
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Misc("DIFF_TERM=TRUE"),
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),
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("ad9154_sync", 1,
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Subsignal("p", Pins("HPC:LA02_P")),
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Subsignal("n", Pins("HPC:LA02_N")),
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IOStandard("LVDS_25"),
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Misc("DIFF_TERM=TRUE"),
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),
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("ad9154_jesd", 0, # AD9154's SERDIN7
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Subsignal("txp", Pins("HPC:DP0_C2M_P")),
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Subsignal("txn", Pins("HPC:DP0_C2M_N"))
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),
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("ad9154_jesd", 1, # AD9154's SERDIN6
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Subsignal("txp", Pins("HPC:DP1_C2M_P")),
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Subsignal("txn", Pins("HPC:DP1_C2M_N"))
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),
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("ad9154_jesd", 2, # AD9154's SERDIN5
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Subsignal("txp", Pins("HPC:DP2_C2M_P")),
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Subsignal("txn", Pins("HPC:DP2_C2M_N"))
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),
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("ad9154_jesd", 3, # AD9154's SERDIN4
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Subsignal("txp", Pins("HPC:DP3_C2M_P")),
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Subsignal("txn", Pins("HPC:DP3_C2M_N"))
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),
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("ad9154_jesd", 4, # AD9154's SERDIN2
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Subsignal("txp", Pins("HPC:DP4_C2M_P")),
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Subsignal("txn", Pins("HPC:DP4_C2M_N"))
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),
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("ad9154_jesd", 5, # AD9154's SERDIN0
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Subsignal("txp", Pins("HPC:DP5_C2M_P")),
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Subsignal("txn", Pins("HPC:DP5_C2M_N"))
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),
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("ad9154_jesd", 6, # AD9154's SERDIN1
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Subsignal("txp", Pins("HPC:DP6_C2M_P")),
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Subsignal("txn", Pins("HPC:DP6_C2M_N"))
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),
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("ad9154_jesd", 7, # AD9154's SERDIN3
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Subsignal("txp", Pins("HPC:DP7_C2M_P")),
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Subsignal("txn", Pins("HPC:DP7_C2M_N"))
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),
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]
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@ -1,271 +0,0 @@
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#!/usr/bin/env python3
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import argparse
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from migen.genlib.cdc import MultiReg
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from jesd204b.common import (JESD204BTransportSettings,
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JESD204BPhysicalSettings,
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JESD204BSettings)
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from jesd204b.phy.gtx import GTXQuadPLL
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from jesd204b.phy import JESD204BPhyTX
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from jesd204b.core import JESD204BCoreTX
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from jesd204b.core import JESD204BCoreTXControl
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from misoc.interconnect.csr import *
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from misoc.cores import gpio
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from misoc.cores import spi as spi_csr
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from misoc.targets.kc705 import MiniSoC, soc_kc705_args, soc_kc705_argdict
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from misoc.integration.builder import builder_args, builder_argdict
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from artiq.gateware.amp import AMPSoC, build_artiq_soc
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from artiq.gateware import rtio
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from artiq.gateware.ad9154_fmc_ebz import ad9154_fmc_ebz
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from artiq.gateware.rtio.phy import (ttl_simple, ttl_serdes_7series,
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sawg)
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from artiq import __version__ as artiq_version
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class _PhaserCRG(Module, AutoCSR):
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def __init__(self, platform, refclk):
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self._clock_sel = CSRStorage()
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self._pll_reset = CSRStorage(reset=1)
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self._pll_locked = CSRStatus()
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self.clock_domains.cd_rtio = ClockDomain()
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self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True)
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external_clk = Signal()
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user_sma_clock = platform.request("user_sma_clock")
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platform.add_period_constraint(user_sma_clock.p, 20/3)
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self.specials += Instance("IBUFDS",
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i_I=user_sma_clock.p, i_IB=user_sma_clock.n,
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o_O=external_clk)
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pll_locked = Signal()
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rtio_clk = Signal()
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rtiox4_clk = Signal()
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self.specials += [
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Instance("PLLE2_ADV",
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p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
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p_REF_JITTER1=0.01, p_REF_JITTER2=0.01,
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p_CLKIN1_PERIOD=20/3, p_CLKIN2_PERIOD=20/3,
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i_CLKIN1=refclk, i_CLKIN2=external_clk,
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# Warning: CLKINSEL=0 means CLKIN2 is selected
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i_CLKINSEL=~self._clock_sel.storage,
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# VCO @ 1.2GHz when using 150MHz input
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p_CLKFBOUT_MULT=8, p_DIVCLK_DIVIDE=1,
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i_CLKFBIN=self.cd_rtio.clk,
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i_RST=self._pll_reset.storage,
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o_CLKFBOUT=rtio_clk,
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p_CLKOUT0_DIVIDE=2, p_CLKOUT0_PHASE=0.0,
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o_CLKOUT0=rtiox4_clk),
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Instance("BUFG", i_I=rtio_clk, o_O=self.cd_rtio.clk),
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Instance("BUFG", i_I=rtiox4_clk, o_O=self.cd_rtiox4.clk),
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AsyncResetSynchronizer(self.cd_rtio, ~pll_locked),
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MultiReg(pll_locked, self._pll_locked.status)
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]
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self.cd_rtio.clk.attr.add("keep")
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platform.add_period_constraint(self.cd_rtio.clk, 20/3)
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class AD9154JESD(Module, AutoCSR):
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def __init__(self, platform):
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self.jreset = CSRStorage(reset=1)
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ps = JESD204BPhysicalSettings(l=4, m=4, n=16, np=16)
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ts = JESD204BTransportSettings(f=2, s=1, k=16, cs=1)
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settings = JESD204BSettings(ps, ts, did=0x5a, bid=0x5)
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linerate = 6e9
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refclk_freq = 150e6
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fabric_freq = 150*1000*1000
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refclk = Signal()
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self.clock_domains.cd_jesd = ClockDomain()
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refclk_pads = platform.request("ad9154_refclk")
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self.specials += [
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Instance("IBUFDS_GTE2", i_CEB=0,
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i_I=refclk_pads.p, i_IB=refclk_pads.n, o_O=refclk),
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Instance("BUFG", i_I=refclk, o_O=self.cd_jesd.clk),
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AsyncResetSynchronizer(self.cd_jesd, self.jreset.storage),
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]
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self.cd_jesd.clk.attr.add("keep")
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platform.add_period_constraint(self.cd_jesd.clk, 1e9/refclk_freq)
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qpll = GTXQuadPLL(refclk, refclk_freq, linerate)
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self.submodules += qpll
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self.phys = []
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for i in range(4):
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||||
phy = JESD204BPhyTX(
|
||||
qpll, platform.request("ad9154_jesd", i), fabric_freq)
|
||||
phy.transmitter.cd_tx.clk.attr.add("keep")
|
||||
platform.add_period_constraint(phy.transmitter.cd_tx.clk,
|
||||
40*1e9/linerate)
|
||||
platform.add_false_path_constraints(self.cd_jesd.clk,
|
||||
phy.transmitter.cd_tx.clk)
|
||||
self.phys.append(phy)
|
||||
to_jesd = ClockDomainsRenamer("jesd")
|
||||
self.submodules.core = to_jesd(JESD204BCoreTX(self.phys, settings,
|
||||
converter_data_width=32))
|
||||
self.submodules.control = to_jesd(JESD204BCoreTXControl(self.core))
|
||||
self.core.register_jsync(platform.request("ad9154_sync"))
|
||||
|
||||
self.comb += [
|
||||
platform.request("ad9154_txen", 0).eq(1),
|
||||
platform.request("ad9154_txen", 1).eq(1),
|
||||
platform.request("user_led", 3).eq(self.core.jsync),
|
||||
]
|
||||
|
||||
# blinking leds for transceiver reset status
|
||||
for i in range(4):
|
||||
counter = Signal(max=fabric_freq)
|
||||
self.comb += platform.request("user_led", 4 + i).eq(counter[-1])
|
||||
sync = getattr(self.sync, "phy{}_tx".format(i))
|
||||
sync += [
|
||||
counter.eq(counter - 1),
|
||||
If(counter == 0,
|
||||
counter.eq(fabric_freq - 1)
|
||||
)
|
||||
]
|
||||
|
||||
|
||||
class AD9154(Module, AutoCSR):
|
||||
def __init__(self, platform):
|
||||
self.submodules.jesd = AD9154JESD(platform)
|
||||
|
||||
self.sawgs = [sawg.Channel(width=16, parallelism=2) for i in range(4)]
|
||||
self.submodules += self.sawgs
|
||||
|
||||
# self.sawgs[0].connect_y(self.sawgs[1])
|
||||
# self.sawgs[1].connect_y(self.sawgs[0])
|
||||
# self.sawgs[2].connect_y(self.sawgs[3])
|
||||
# self.sawgs[3].connect_y(self.sawgs[2])
|
||||
|
||||
for conv, ch in zip(self.jesd.core.sink.flatten(), self.sawgs):
|
||||
self.sync.jesd += conv.eq(Cat(ch.o))
|
||||
|
||||
|
||||
class Phaser(MiniSoC, AMPSoC):
|
||||
mem_map = {
|
||||
"cri_con": 0x10000000,
|
||||
"rtio": 0x20000000,
|
||||
"rtio_dma": 0x30000000,
|
||||
"mailbox": 0x70000000,
|
||||
"ad9154": 0x50000000,
|
||||
}
|
||||
mem_map.update(MiniSoC.mem_map)
|
||||
|
||||
def __init__(self, cpu_type="or1k", **kwargs):
|
||||
MiniSoC.__init__(self,
|
||||
cpu_type=cpu_type,
|
||||
sdram_controller_type="minicon",
|
||||
l2_size=128*1024,
|
||||
ident=artiq_version,
|
||||
ethmac_nrxslots=4,
|
||||
ethmac_ntxslots=4,
|
||||
**kwargs)
|
||||
AMPSoC.__init__(self)
|
||||
self.platform.toolchain.bitstream_commands.extend([
|
||||
"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
|
||||
])
|
||||
|
||||
platform = self.platform
|
||||
platform.add_extension(ad9154_fmc_ebz)
|
||||
|
||||
self.submodules.leds = gpio.GPIOOut(Cat(
|
||||
platform.request("user_led", 0),
|
||||
platform.request("user_led", 1)))
|
||||
self.csr_devices.append("leds")
|
||||
|
||||
i2c = platform.request("i2c")
|
||||
self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
|
||||
self.csr_devices.append("i2c")
|
||||
self.config["I2C_BUS_COUNT"] = 1
|
||||
|
||||
ad9154_spi = platform.request("ad9154_spi")
|
||||
self.comb += ad9154_spi.en.eq(1)
|
||||
self.submodules.converter_spi = spi_csr.SPIMaster(ad9154_spi)
|
||||
self.csr_devices.append("converter_spi")
|
||||
self.config["HAS_AD9516"] = None
|
||||
self.config["CONVERTER_SPI_AD9516_CS"] = 1
|
||||
self.config["CONVERTER_SPI_FIRST_AD9154_CS"] = 0
|
||||
|
||||
self.submodules.ad9154_0 = AD9154(platform)
|
||||
self.csr_devices.append("ad9154_0")
|
||||
self.config["HAS_AD9154"] = None
|
||||
self.add_csr_group("ad9154", ["ad9154_0"])
|
||||
|
||||
rtio_channels = []
|
||||
|
||||
phy = ttl_serdes_7series.InOut_8X(
|
||||
platform.request("user_sma_gpio_n"))
|
||||
self.submodules += phy
|
||||
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=128))
|
||||
|
||||
phy = ttl_simple.Output(platform.request("user_led", 2))
|
||||
self.submodules += phy
|
||||
rtio_channels.append(rtio.Channel.from_phy(phy))
|
||||
|
||||
sysref_pads = platform.request("ad9154_sysref")
|
||||
phy = ttl_serdes_7series.Input_8X(sysref_pads.p, sysref_pads.n)
|
||||
self.submodules += phy
|
||||
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=32,
|
||||
ofifo_depth=2))
|
||||
|
||||
self.config["RTIO_FIRST_SAWG_CHANNEL"] = len(rtio_channels)
|
||||
rtio_channels.extend(rtio.Channel.from_phy(phy)
|
||||
for sawg in self.ad9154_0.sawgs
|
||||
for phy in sawg.phys)
|
||||
|
||||
self.config["HAS_RTIO_LOG"] = None
|
||||
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
|
||||
rtio_channels.append(rtio.LogChannel())
|
||||
|
||||
self.submodules.rtio_crg = _PhaserCRG(
|
||||
platform, self.ad9154_0.jesd.cd_jesd.clk)
|
||||
self.csr_devices.append("rtio_crg")
|
||||
self.submodules.rtio_core = rtio.Core(rtio_channels)
|
||||
self.csr_devices.append("rtio_core")
|
||||
self.submodules.rtio = rtio.KernelInitiator()
|
||||
self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(
|
||||
rtio.DMA(self.get_native_sdram_if()))
|
||||
self.register_kernel_cpu_csrdevice("rtio")
|
||||
self.register_kernel_cpu_csrdevice("rtio_dma")
|
||||
self.submodules.cri_con = rtio.CRIInterconnectShared(
|
||||
[self.rtio.cri, self.rtio_dma.cri],
|
||||
[self.rtio_core.cri])
|
||||
self.register_kernel_cpu_csrdevice("cri_con")
|
||||
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
|
||||
self.csr_devices.append("rtio_moninj")
|
||||
self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio_core.cri,
|
||||
self.get_native_sdram_if())
|
||||
self.csr_devices.append("rtio_analyzer")
|
||||
|
||||
platform.add_false_path_constraints(
|
||||
self.crg.cd_sys.clk, self.rtio_crg.cd_rtio.clk)
|
||||
platform.add_false_path_constraints(
|
||||
self.crg.cd_sys.clk, self.ad9154_0.jesd.cd_jesd.clk)
|
||||
for phy in self.ad9154_0.jesd.phys:
|
||||
platform.add_false_path_constraints(
|
||||
self.crg.cd_sys.clk, phy.transmitter.cd_tx.clk)
|
||||
|
||||
|
||||
def main():
|
||||
parser = argparse.ArgumentParser(
|
||||
description="ARTIQ device binary builder / KC705 phaser demo")
|
||||
builder_args(parser)
|
||||
soc_kc705_args(parser)
|
||||
args = parser.parse_args()
|
||||
|
||||
soc = Phaser(**soc_kc705_argdict(args))
|
||||
build_artiq_soc(soc, builder_argdict(args))
|
||||
|
||||
|
||||
if __name__ == "__main__":
|
||||
main()
|
||||
|
|
@ -1,12 +0,0 @@
|
|||
#!/bin/bash
|
||||
|
||||
BUILD_SETTINGS_FILE=$HOME/.m-labs/build_settings.sh
|
||||
[ -f $BUILD_SETTINGS_FILE ] && . $BUILD_SETTINGS_FILE
|
||||
|
||||
SOC_PREFIX=$PREFIX/lib/python3.5/site-packages/artiq/binaries/kc705-phaser
|
||||
mkdir -p $SOC_PREFIX
|
||||
|
||||
V=1 $PYTHON -m artiq.gateware.targets.phaser --toolchain vivado $MISOC_EXTRA_VIVADO_CMDLINE
|
||||
cp misoc_phaser_kc705/gateware/top.bit $SOC_PREFIX
|
||||
cp misoc_phaser_kc705/software/bios/bios.bin $SOC_PREFIX
|
||||
cp misoc_phaser_kc705/software/runtime/runtime.fbi $SOC_PREFIX
|
||||
|
|
@ -1,23 +0,0 @@
|
|||
package:
|
||||
name: artiq-kc705-phaser
|
||||
version: {{ environ.get("GIT_DESCRIBE_TAG", "") }}
|
||||
|
||||
source:
|
||||
git_url: ../..
|
||||
|
||||
build:
|
||||
noarch: generic
|
||||
ignore_prefix_files: True
|
||||
number: {{ environ.get("GIT_DESCRIBE_NUMBER", 0) }}
|
||||
string: py_{{ environ.get("GIT_DESCRIBE_NUMBER", 0) }}+git{{ environ.get("GIT_FULL_HASH", "")[:8] }}
|
||||
|
||||
requirements:
|
||||
build:
|
||||
- artiq-dev {{ "{tag} py_{number}+git{hash}".format(tag=environ.get("GIT_DESCRIBE_TAG"), number=environ.get("GIT_DESCRIBE_NUMBER"), hash=environ.get("GIT_FULL_HASH", "")[:8]) if "GIT_DESCRIBE_TAG" in environ else "" }}
|
||||
run:
|
||||
- artiq {{ "{tag} py_{number}+git{hash}".format(tag=environ.get("GIT_DESCRIBE_TAG"), number=environ.get("GIT_DESCRIBE_NUMBER"), hash=environ.get("GIT_FULL_HASH", "")[:8]) if "GIT_DESCRIBE_TAG" in environ else "" }}
|
||||
|
||||
about:
|
||||
home: https://m-labs.hk/artiq
|
||||
license: LGPL
|
||||
summary: 'Bitstream, BIOS and runtime for Phaser on the KC705 board'
|
||||
|
|
@ -144,87 +144,3 @@ The QC2 hardware uses TCA6424A I2C I/O expanders to define the directions of its
|
|||
To avoid I/O contention, the startup kernel should first program the TCA6424A expanders and then call ``output()`` on all ``TTLInOut`` channels that should be configured as outputs.
|
||||
|
||||
See :mod:`artiq.coredevice.i2c` for more details.
|
||||
|
||||
|
||||
.. _phaser:
|
||||
|
||||
Phaser
|
||||
++++++
|
||||
|
||||
The Phaser adapter is an AD9154-FMC-EBZ, a 4 channel 2.4 GHz DAC on an FMC HPC card.
|
||||
|
||||
Phaser is a proof-of-concept design of a GHz-datarate, multi-channel, interpolating, multi-tone, direct digital synthesizer (DDS) compatible with ARTIQ's RTIO channels.
|
||||
Ultimately it will be the basis for the ARTIQ Sayma Smart Arbitrary Waveform Generator project. See https://github.com/m-labs/sinara.
|
||||
|
||||
*Features*:
|
||||
|
||||
* up to 4 channels
|
||||
* up to 500 MHz data rate per channel (KC705 limitation)
|
||||
* up to 8x interpolation to 2.4 GHz DAC sample rate
|
||||
* Real-time sample-coherent control over amplitude, frequency, phase of each channel through ARTIQ RTIO commands
|
||||
* Full configurability of the AD9154 and AD9516 through SPI with ARTIQ kernel support
|
||||
* All SPI registers and register bits exposed as human readable names
|
||||
* Parametrized JESD204B core (also capable of operation with eight lanes)
|
||||
* The code can be reconfigured. Possible example configurations are: support 2 channels at 1 GHz datarate, support 4 channels at 300 MHz data rate, no interpolation, and using mix mode to stress the second and third Nyquist zones (150-300 MHz and 300-450 MHz). Please contact M-Labs if you need help with this.
|
||||
|
||||
The hardware required is a KC705 with an AD9154-FMC-EBZ plugged into the HPC connector and a low-noise sample rate reference clock.
|
||||
|
||||
This work was supported by the Army Research Lab and the University of Maryland.
|
||||
|
||||
Installation
|
||||
............
|
||||
|
||||
These installation instructions are a short form of those in the ARTIQ manual.
|
||||
|
||||
* See the chapter on setting up a :ref:`development environment <develop-from-conda>`.
|
||||
* When compiling the binaries, use the ``phaser`` target: ``python -m artiq.gateware.targets.phaser``
|
||||
* From time to time and on request there may be pre-built binaries in the ``artiq-kc705-phaser`` package on the M-Labs conda package label.
|
||||
|
||||
Setup
|
||||
.....
|
||||
|
||||
* Setup the KC705 (jumpers, etc.) observing the ARTIQ manual. VADJ does not need to be changed.
|
||||
* On the AD9154-FMC-EBZ put jumpers:
|
||||
|
||||
- on XP1, between pin 5 and 6 (will keep the PIC in reset)
|
||||
- on JP3 (will force output enable on FXLA108)
|
||||
|
||||
* Refer to the ARTIQ documentation to configure the MAC and IP addresses and other settings. If the board was running stock ARTIQ before, the settings will be kept.
|
||||
* A 300 MHz clock of roughly 10 dBm (0.2 to 3.4 V peak-to-peak into 50 Ohm) must be connected to the AD9154-FMC-EBZ J1. The input is 50 Ohm terminated. The RTIO clock, DAC deviceclock, FPGA deviceclock, and SYSREF are derived from this signal.
|
||||
* The RTIO coarse clock (the rate of the RTIO timestamp counter) is 150 MHz. The RTIO ``ref_period`` is 1/150 MHz = 5ns/6. The RTIO ``ref_multiplier`` is ``8``. C.f. ``device_db.py`` for both variables. The JED204B DAC data rate and DAC device clock are both 300 MHz. The JESD204B line rate is 6 GHz.
|
||||
* Configure an oscilloscope to trigger at 0.5 V on rising edge of ttl_sma (user_gpio_n on the KC705 board). Monitor DAC0 (J17) on the oscilloscope set for 100 mV/div and 200 ns/div.
|
||||
* An example device database, several status and test scripts are provided in ``artiq/examples/phaser/``. ::
|
||||
|
||||
cd artiq/examples/phaser
|
||||
|
||||
* Edit ``device_db.py`` to match the hostname or IP address of the core device.
|
||||
* Use ``ping`` and ``flterm`` to verify that the core device starts up and boots correctly.
|
||||
|
||||
Usage
|
||||
.....
|
||||
|
||||
* Run ``artiq_run repository/demo.py`` for an example that exercises several different use cases of synchronized phase, amplitude, and frequency updates.
|
||||
for an example that exercises several different use cases of synchronized phase, amplitude, and frequency updates.
|
||||
* Run ``artiq_run repository/demo_2tone.py`` for an example that emits a shaped two-tone pulse.
|
||||
* Implement your own experiments using the SAWG channels.
|
||||
* Verify clock stability between the sample rate reference clock and the DAC outputs.
|
||||
|
||||
RTIO channels
|
||||
.............
|
||||
|
||||
+--------------+------------+--------------+
|
||||
| RTIO channel | TTL line | Capability |
|
||||
+==============+============+==============+
|
||||
| 0 | SMA_GPIO_N | Input+Output |
|
||||
+--------------+------------+--------------+
|
||||
| 1 | LED | Output |
|
||||
+--------------+------------+--------------+
|
||||
| 2 | SYSREF | Input |
|
||||
+--------------+------------+--------------+
|
||||
| 3 | SYNC | Input |
|
||||
+--------------+------------+--------------+
|
||||
|
||||
The SAWG channels start with RTIO channel number 3, each SAWG channel occupying 10 RTIO channels.
|
||||
|
||||
The board has one non-RTIO SPI bus that is accessible through
|
||||
:mod:`artiq.coredevice.ad9154`.
|
||||
|
|
|
|||
Loading…
Reference in New Issue