From 5612b318605be1057f21cd91b3087ce994c3d265 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sun, 6 Oct 2019 16:15:24 +0800 Subject: [PATCH] sayma_rtm_drtio: add HMC clock chip and DAC control --- artiq/gateware/targets/sayma_rtm_drtio.py | 26 +++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/artiq/gateware/targets/sayma_rtm_drtio.py b/artiq/gateware/targets/sayma_rtm_drtio.py index 08d0589f3..415948fcd 100755 --- a/artiq/gateware/targets/sayma_rtm_drtio.py +++ b/artiq/gateware/targets/sayma_rtm_drtio.py @@ -10,6 +10,7 @@ from migen.genlib.cdc import MultiReg from misoc.interconnect.csr import * from misoc.cores import gpio +from misoc.cores import spi2 from misoc.cores.a7_gtp import * from misoc.targets.sayma_rtm import BaseSoC, soc_sayma_rtm_args, soc_sayma_rtm_argdict from misoc.integration.builder import Builder, builder_args, builder_argdict @@ -165,6 +166,31 @@ class _SatelliteBase(BaseSoC): self.csr_devices.append("rtio_crg") fix_serdes_timing_path(platform) + # HMC clock chip and DAC control + self.comb += platform.request("ad9154_rst_n", 0).eq(1) + if self.hw_rev == "v2.0": + self.comb += platform.request("ad9154_rst_n", 1).eq(1) + self.submodules.converter_spi = spi2.SPIMaster(spi2.SPIInterface( + platform.request("hmc_spi"), + platform.request("ad9154_spi", 0), + platform.request("ad9154_spi", 1))) + self.csr_devices.append("converter_spi") + self.submodules.hmc7043_reset = gpio.GPIOOut( + platform.request("hmc7043_reset"), reset_out=1) + self.csr_devices.append("hmc7043_reset") + self.submodules.hmc7043_gpo = gpio.GPIOIn( + platform.request("hmc7043_gpo")) + self.csr_devices.append("hmc7043_gpo") + if self.hw_rev == "v2.0": + self.comb += platform.request("hmc830_pwr_en").eq(1) + self.submodules.hmc7043_out_en = gpio.GPIOOut( + platform.request("hmc7043_out_en")) + self.csr_devices.append("hmc7043_out_en") + self.config["HAS_HMC830_7043"] = None + self.config["CONVERTER_SPI_HMC830_CS"] = 0 + self.config["CONVERTER_SPI_HMC7043_CS"] = 1 + self.config["HMC830_REF"] = "150" + def add_rtio(self, rtio_channels): self.submodules.rtio_moninj = rtio.MonInj(rtio_channels) self.csr_devices.append("rtio_moninj")