occheung
/
artiq
forked from M-Labs/artiq
1
0
Fork 0
Code Pull Requests Activity

sayma_amc: add DRTIO transceiver on rtm_amc_link for v2 hardware

This commit is contained in:
Sebastien Bourdeauducq 2019-03-23 13:41:22 +08:00
parent bbb8c00518
commit 560849e693
1 changed files with 4 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
artiq/gateware/targets/sayma_amc.py
View File

@ -522,10 +522,13 @@ class Satellite(BaseSoC, RTMCommon):
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels) self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
self.csr_devices.append("rtio_moninj") self.csr_devices.append("rtio_moninj")
drtio_data_pads = [platform.request("sfp", 0)]
if self.hw_rev == "v2.0":
drtio_data_pads.append(platform.request("rtm_amc_link"))
self.comb += platform.request("sfp_tx_disable", 0).eq(0) self.comb += platform.request("sfp_tx_disable", 0).eq(0)
self.submodules.drtio_transceiver = gth_ultrascale.GTH( self.submodules.drtio_transceiver = gth_ultrascale.GTH(
clock_pads=platform.request("cdr_clk_clean"), clock_pads=platform.request("cdr_clk_clean"),
data_pads=[platform.request("sfp", 0)], data_pads=drtio_data_pads,
sys_clk_freq=self.clk_freq, sys_clk_freq=self.clk_freq,
rtio_clk_freq=rtio_clk_freq) rtio_clk_freq=rtio_clk_freq)
self.csr_devices.append("drtio_transceiver") self.csr_devices.append("drtio_transceiver")