diff --git a/artiq/gateware/serwb/datapath.py b/artiq/gateware/serwb/datapath.py
index 9d7f0bb19..f91cd602f 100644
--- a/artiq/gateware/serwb/datapath.py
+++ b/artiq/gateware/serwb/datapath.py
@@ -185,11 +185,13 @@ class RXDatapath(Module):
             ]
 
         # idle decoding
-        idle_timer = WaitTimer(256)
+        idle_timer = WaitTimer(32)
         self.submodules += idle_timer
-        self.comb += [
-            idle_timer.wait.eq(1),
-            idle.eq(idle_timer.done & ((converter.source.data == 0) | (converter.source.data == (2**40-1))))
+        self.sync += [
+            If(converter.source.stb,
+                idle_timer.wait.eq((converter.source.data == 0) | (converter.source.data == (2**40-1)))
+            ),
+            idle.eq(idle_timer.done)
         ]
         # comma decoding
         self.sync += \
diff --git a/artiq/gateware/serwb/genphy.py b/artiq/gateware/serwb/genphy.py
index e3d2d3fbd..b9d6c02f2 100644
--- a/artiq/gateware/serwb/genphy.py
+++ b/artiq/gateware/serwb/genphy.py
@@ -313,7 +313,9 @@ class SERWBPHY(Module, AutoCSR):
         # tx/rx dataflow
         self.comb += [
             If(self.init.ready,
-                sink.connect(self.serdes.tx.sink),
+                If(sink.stb,
+                    sink.connect(self.serdes.tx.sink),
+                ),
                 self.serdes.rx.source.connect(source)
             ).Else(
                 self.serdes.rx.source.ack.eq(1)
diff --git a/artiq/gateware/serwb/phy.py b/artiq/gateware/serwb/phy.py
index efb2463e2..d878cfb17 100644
--- a/artiq/gateware/serwb/phy.py
+++ b/artiq/gateware/serwb/phy.py
@@ -362,7 +362,9 @@ class SERWBPHY(Module, AutoCSR):
         # tx/rx dataflow
         self.comb += [
             If(self.init.ready,
-                sink.connect(self.serdes.tx.sink),
+                If(sink.stb,
+                    sink.connect(self.serdes.tx.sink),
+                ),
                 self.serdes.rx.source.connect(source)
             ).Else(
                 self.serdes.rx.source.ack.eq(1)