forked from M-Labs/artiq
kernel_cpu: disable PCU
* contributes to long timing paths on artix 7 (kasli) * currently only used for testing and debugging
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@ -25,9 +25,7 @@ class KernelCPU(Module):
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self.submodules.cpu = ClockDomainsRenamer("sys_kernel")(
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self.submodules.cpu = ClockDomainsRenamer("sys_kernel")(
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mor1kx.MOR1KX(
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mor1kx.MOR1KX(
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platform,
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platform,
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OPTION_RESET_PC=exec_address,
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OPTION_RESET_PC=exec_address))
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FEATURE_PERFCOUNTERS="ENABLED",
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OPTION_PERFCOUNTERS_NUM=7))
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# DRAM access
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# DRAM access
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self.wb_sdram = wishbone.Interface()
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self.wb_sdram = wishbone.Interface()
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