occheung
/
artiq
forked from M-Labs/artiq
1
0
Fork 0
Code Pull Requests Activity

doc/dds: fix init timing margin

This commit is contained in:
Sebastien Bourdeauducq 2016-03-29 12:01:22 +08:00
parent ce57794e7f
commit 50888865e7
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
artiq/coredevice/dds.py
View File

@ -145,7 +145,7 @@ class _DDSGeneric:
This function cannot be used in a batch; the correct way of
initializing multiple DDS channels is to call this function
sequentially with a delay between the calls. 500us provides a good
sequentially with a delay between the calls. 2ms provides a good
timing margin."""
dds_init(now_mu(), self.bus_channel, self.channel)