From 5046d6a529cbd432ffa58afa6db462f9e68d58d1 Mon Sep 17 00:00:00 2001
From: Robert Jordens <jordens@gmail.com>
Date: Mon, 26 Feb 2018 18:53:39 +0000
Subject: [PATCH] ad9912/10: add a bit more slack to init()

---
 artiq/coredevice/ad9910.py |  6 +++---
 artiq/coredevice/ad9912.py | 10 +++++-----
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/artiq/coredevice/ad9910.py b/artiq/coredevice/ad9910.py
index ff2c35070..06ddfee67 100644
--- a/artiq/coredevice/ad9910.py
+++ b/artiq/coredevice/ad9910.py
@@ -132,15 +132,15 @@ class AD9910:
         """
         # Set SPI mode
         self.write32(_AD9910_REG_CFR1, 0x00000002)
-        self.cpld.io_update.pulse(1*us)
+        self.cpld.io_update.pulse(2*us)
         # Use the AUX DAC setting to identify and confirm presence
         aux_dac = self.read32(_AD9910_REG_AUX_DAC)
         if aux_dac & 0xff != 0x7f:
             raise ValueError("Urukul AD9910 AUX_DAC mismatch")
-        delay(20*us)  # slack
+        delay(50*us)  # slack
         # Configure PLL settings and bring up PLL
         self.write32(_AD9910_REG_CFR2, 0x01400020)
-        self.cpld.io_update.pulse(1*us)
+        self.cpld.io_update.pulse(2*us)
         cfr3 = (0x0807c100 | (self.pll_vco << 24) |
                 (self.pll_cp << 19) | (self.pll_n << 1))
         self.write32(_AD9910_REG_CFR3, cfr3 | 0x400)  # PFD reset
diff --git a/artiq/coredevice/ad9912.py b/artiq/coredevice/ad9912.py
index bc12192d6..fbf116e05 100644
--- a/artiq/coredevice/ad9912.py
+++ b/artiq/coredevice/ad9912.py
@@ -92,20 +92,20 @@ class AD9912:
         """
         # SPI mode
         self.write(AD9912_SER_CONF, 0x99, length=1)
-        self.cpld.io_update.pulse(1*us)
+        self.cpld.io_update.pulse(2*us)
         # Verify chip ID and presence
         prodid = self.read(AD9912_PRODIDH, length=2)
         if (prodid != 0x1982) and (prodid != 0x1902):
             raise ValueError("Urukul AD9912 product id mismatch")
-        delay(30*us)
+        delay(50*us)
         # HSTL power down, CMOS power down
         self.write(AD9912_PWRCNTRL1, 0x80, length=1)
-        self.cpld.io_update.pulse(1*us)
+        self.cpld.io_update.pulse(2*us)
         self.write(AD9912_N_DIV, self.pll_n//2 - 2, length=1)
-        self.cpld.io_update.pulse(1*us)
+        self.cpld.io_update.pulse(2*us)
         # I_cp = 375 µA, VCO high range
         self.write(AD9912_PLLCFG, 0b00000101, length=1)
-        self.cpld.io_update.pulse(1*us)
+        self.cpld.io_update.pulse(2*us)
 
     @kernel
     def set_att_mu(self, att):