forked from M-Labs/artiq
sayma: disable Urukul and Zotino for now
Ultrascale I/Os are being a pain as usual and the SPI core won't compile.
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8335085fd6
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4fdc20bb11
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@ -474,12 +474,12 @@ class Master(MiniSoC, AMPSoC):
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phy = ttl_simple.Output(s)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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eem.Urukul.add_std(self, 1, 0, ttl_simple.Output,
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iostandard="LVDS")
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#eem.Urukul.add_std(self, 1, 0, ttl_simple.Output,
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# iostandard="LVDS")
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eem.DIO.add_std(self, 2, ttl_simple.Output, ttl_simple.Output,
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iostandard="LVDS")
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eem.Zotino.add_std(self, 3, ttl_simple.Output,
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iostandard="LVDS")
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#eem.Zotino.add_std(self, 3, ttl_simple.Output,
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# iostandard="LVDS")
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self.config["HAS_RTIO_LOG"] = None
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self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
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