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gateware: increase RTIO FIFO sizes for NIST_CLOCK. Closes #623

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David Leibrandt 2016-11-20 15:17:38 +08:00 committed by Sebastien Bourdeauducq
parent 2015fe9de0
commit 4a62e09bd4
1 changed files with 4 additions and 4 deletions
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8
artiq/gateware/targets/kc705.py
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@ -230,16 +230,16 @@ class NIST_CLOCK(_NIST_Ions):
if i % 4 == 3:
phy = ttl_serdes_7series.Inout_8X(platform.request("ttl", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=1024))
else:
phy = ttl_serdes_7series.Output_8X(platform.request("ttl", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=1024))
for i in range(2):
phy = ttl_serdes_7series.Inout_8X(platform.request("pmt", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=16384))
phy = ttl_serdes_7series.Inout_8X(platform.request("user_sma_gpio_n_33"))
self.submodules += phy
@ -279,7 +279,7 @@ class NIST_CLOCK(_NIST_Ions):
phy = dds.AD9914(platform.request("dds"), 11, onehot=True)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy,
ofifo_depth=512,
ofifo_depth=16384,
ififo_depth=4))
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)