diff --git a/artiq/coredevice/ad9910.py b/artiq/coredevice/ad9910.py
index ff57fa28f..e6b5309fb 100644
--- a/artiq/coredevice/ad9910.py
+++ b/artiq/coredevice/ad9910.py
@@ -133,12 +133,12 @@ class AD9910:
         value from a I2C EEPROM; in which case, `sync_delay_seed` must be set
         to the same string value.
     """
-    kernel_invariants = {"chip_select", "cpld", "core", "bus",
-                         "ftw_per_hz", "sysclk_per_mu"}
 
     def __init__(self, dmgr, chip_select, cpld_device, sw_device=None,
                  pll_n=40, pll_cp=7, pll_vco=5, sync_delay_seed=-1,
                  io_update_delay=0, pll_en=1):
+        self.kernel_invariants = {"chip_select", "cpld", "core", "bus",
+                                  "ftw_per_hz", "sysclk_per_mu"}
         self.cpld = dmgr.get(cpld_device)
         self.core = self.cpld.core
         self.bus = self.cpld.bus
diff --git a/artiq/coredevice/ad9912.py b/artiq/coredevice/ad9912.py
index 13cf1a121..cdaaa6a8e 100644
--- a/artiq/coredevice/ad9912.py
+++ b/artiq/coredevice/ad9912.py
@@ -26,10 +26,11 @@ class AD9912:
         is the reference clock divider (both set in the parent Urukul CPLD
         instance).
     """
-    kernel_invariants = {"chip_select", "cpld", "core", "bus", "ftw_per_hz"}
 
     def __init__(self, dmgr, chip_select, cpld_device, sw_device=None,
                  pll_n=10):
+        self.kernel_invariants = {"chip_select", "cpld", "core", "bus",
+                                  "ftw_per_hz"}
         self.cpld = dmgr.get(cpld_device)
         self.core = self.cpld.core
         self.bus = self.cpld.bus