From 49f7a1610f47b11e32286e3120970ec782ff2c1b Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Tue, 7 Aug 2018 20:53:14 +0800 Subject: [PATCH] sayma: use GTP_CLK1 only for all variants (#1080) --- artiq/firmware/libboard_artiq/hmc830_7043.rs | 5 +---- artiq/gateware/jesd204_tools.py | 2 +- artiq/gateware/targets/sayma_amc.py | 11 +++++------ 3 files changed, 7 insertions(+), 11 deletions(-) diff --git a/artiq/firmware/libboard_artiq/hmc830_7043.rs b/artiq/firmware/libboard_artiq/hmc830_7043.rs index acb8af556..f0a67e86d 100644 --- a/artiq/firmware/libboard_artiq/hmc830_7043.rs +++ b/artiq/firmware/libboard_artiq/hmc830_7043.rs @@ -169,12 +169,9 @@ pub mod hmc7043 { (true, SYSREF_DIV, 0x08), // 3: DAC1_SYSREF (false, 0, 0x08), // 4: ADC2_CLK (false, 0, 0x08), // 5: ADC2_SYSREF - (true, FPGA_CLK_DIV, 0x08), // 6: GTP_CLK2 + (false, 0, 0x08), // 6: GTP_CLK2 (true, SYSREF_DIV, 0x10), // 7: FPGA_DAC_SYSREF, LVDS -#[cfg(hmc7043_enable_clk1)] (true, FPGA_CLK_DIV, 0x08), // 8: GTP_CLK1 -#[cfg(not(hmc7043_enable_clk1))] - (false, 0, 0x08), // 8: GTP_CLK1 (false, 0, 0x10), // 9: AMC_MASTER_AUX_CLK (false, 0, 0x10), // 10: RTM_MASTER_AUX_CLK (true, FPGA_CLK_DIV, 0x10), // 11: FPGA_ADC_SYSREF, LVDS -- repurposed for siphaser diff --git a/artiq/gateware/jesd204_tools.py b/artiq/gateware/jesd204_tools.py index 8187e4999..167a05f3a 100644 --- a/artiq/gateware/jesd204_tools.py +++ b/artiq/gateware/jesd204_tools.py @@ -27,7 +27,7 @@ class UltrascaleCRG(Module, AutoCSR): self.clock_domains.cd_jesd = ClockDomain() refclk2 = Signal() - refclk_pads = platform.request("dac_refclk", 1) + refclk_pads = platform.request("dac_refclk", 0) platform.add_period_constraint(refclk_pads.p, 1e9/self.refclk_freq) self.specials += [ Instance("IBUFDS_GTE3", i_CEB=self.ibuf_disable.storage, p_REFCLK_HROW_CK_SEL=0b00, diff --git a/artiq/gateware/targets/sayma_amc.py b/artiq/gateware/targets/sayma_amc.py index 99af7073e..6e7872278 100755 --- a/artiq/gateware/targets/sayma_amc.py +++ b/artiq/gateware/targets/sayma_amc.py @@ -269,17 +269,19 @@ class MasterDAC(MiniSoC, AMPSoC, RTMCommon): "IBUFDS_GTE3", i_CEB=0, i_I=si5324_clkout.p, i_IB=si5324_clkout.n, attr={("DONT_TOUCH", "true")}) + self.submodules.ad9154_crg = jesd204_tools.UltrascaleCRG(platform) + self.csr_devices.append("ad9154_crg") + self.comb += [ platform.request("sfp_tx_disable", i).eq(0) for i in range(2) ] self.submodules.drtio_transceiver = gth_ultrascale.GTH( - clock_pads=platform.request("dac_refclk", 0), + clock_pads=self.ad9154_crg.refclk, data_pads=[platform.request("sfp", i) for i in range(2)], sys_clk_freq=self.clk_freq, rtio_clk_freq=rtio_clk_freq) self.csr_devices.append("drtio_transceiver") - self.config["HMC7043_ENABLE_CLK1"] = None drtio_csr_group = [] drtio_memory_group = [] @@ -332,14 +334,12 @@ class MasterDAC(MiniSoC, AMPSoC, RTMCommon): self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) - self.submodules.ad9154_crg = jesd204_tools.UltrascaleCRG(platform) if with_sawg: cls = AD9154 else: cls = AD9154NoSAWG self.submodules.ad9154_0 = cls(platform, self.crg, self.ad9154_crg, 0) self.submodules.ad9154_1 = cls(platform, self.crg, self.ad9154_crg, 1) - self.csr_devices.append("ad9154_crg") self.csr_devices.append("ad9154_0") self.csr_devices.append("ad9154_1") self.config["HAS_AD9154"] = None @@ -577,12 +577,11 @@ class Satellite(BaseSoC, RTMCommon): self.comb += platform.request("sfp_tx_disable", 0).eq(0) self.submodules.drtio_transceiver = gth_ultrascale.GTH( - clock_pads=platform.request("dac_refclk", 0), + clock_pads=self.ad9154_crg.refclk, data_pads=[platform.request("sfp", 0)], sys_clk_freq=self.clk_freq, rtio_clk_freq=rtio_clk_freq) self.csr_devices.append("drtio_transceiver") - self.config["HMC7043_ENABLE_CLK1"] = None rx0 = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"}) self.submodules.rx_synchronizer = rx0(XilinxRXSynchronizer())