forked from M-Labs/artiq
sayma: add comments about CPLL line rate on KU GTH
This commit is contained in:
parent
8cd794e9f4
commit
43ecb3fea6
|
@ -192,6 +192,8 @@ class SatelliteBase(MiniSoC):
|
||||||
# JESD204 DAC Channel Group
|
# JESD204 DAC Channel Group
|
||||||
class JDCGSAWG(Module, AutoCSR):
|
class JDCGSAWG(Module, AutoCSR):
|
||||||
def __init__(self, platform, sys_crg, jesd_crg, dac):
|
def __init__(self, platform, sys_crg, jesd_crg, dac):
|
||||||
|
# Kintex Ultrascale GTH, speed grade -1C:
|
||||||
|
# CPLL linerate (D=1): 4.0 - 8.5 Gb/s
|
||||||
self.submodules.jesd = jesd204_tools.UltrascaleTX(
|
self.submodules.jesd = jesd204_tools.UltrascaleTX(
|
||||||
platform, sys_crg, jesd_crg, dac)
|
platform, sys_crg, jesd_crg, dac)
|
||||||
|
|
||||||
|
|
Loading…
Reference in New Issue