occheung
/
artiq
forked from M-Labs/artiq
1
0
Fork 0
Code Pull Requests Activity

sayma: add comments about CPLL line rate on KU GTH

This commit is contained in:
Harry Ho 2020-12-15 18:06:02 +08:00 committed by Sébastien Bourdeauducq
parent 8cd794e9f4
commit 43ecb3fea6
1 changed files with 2 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
artiq/gateware/targets/sayma_amc.py
View File

@ -192,6 +192,8 @@ class SatelliteBase(MiniSoC):
# JESD204 DAC Channel Group
class JDCGSAWG(Module, AutoCSR):
def __init__(self, platform, sys_crg, jesd_crg, dac):
# Kintex Ultrascale GTH, speed grade -1C:
# CPLL linerate (D=1): 4.0 - 8.5 Gb/s
self.submodules.jesd = jesd204_tools.UltrascaleTX(
platform, sys_crg, jesd_crg, dac)