From 4148efd2eeea9da4aaca271d4603128529ab4838 Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Mon, 9 Dec 2019 11:47:29 +0800
Subject: [PATCH] wrpll: implement filters and connect to Si549

---
 artiq/gateware/drtio/wrpll/core.py | 15 +++++++++++++--
 artiq/gateware/drtio/wrpll/thls.py |  7 +++++++
 2 files changed, 20 insertions(+), 2 deletions(-)

diff --git a/artiq/gateware/drtio/wrpll/core.py b/artiq/gateware/drtio/wrpll/core.py
index 37467008a..35902d752 100644
--- a/artiq/gateware/drtio/wrpll/core.py
+++ b/artiq/gateware/drtio/wrpll/core.py
@@ -5,6 +5,7 @@ from misoc.interconnect.csr import *
 
 from artiq.gateware.drtio.wrpll.si549 import Si549
 from artiq.gateware.drtio.wrpll.ddmtd import DDMTD
+from artiq.gateware.drtio.wrpll import thls, filters
 
 
 class FrequencyCounter(Module, AutoCSR):
@@ -48,12 +49,22 @@ class WRPLL(Module, AutoCSR):
             AsyncResetSynchronizer(self.cd_helper, self.helper_reset.storage)
         ]
 
-        self.submodules.main_dcxo = Si549(main_dcxo_i2c)
         self.submodules.helper_dcxo = Si549(helper_dxco_i2c)
+        self.submodules.main_dcxo = Si549(main_dcxo_i2c)
 
-        self.submodules.helper_frequency = FrequencyCounter()
+        self.submodules.helper_frequency = FrequencyCounter()  # for diagnostics
 
         ddmtd_counter = Signal(N)
         self.sync.helper += ddmtd_counter.eq(ddmtd_counter + 1)
         self.submodules.ddmtd_helper = DDMTD(ddmtd_counter, ddmtd_inputs.rec_clk)
         self.submodules.ddmtd_main = DDMTD(ddmtd_counter, ddmtd_inputs.main_xo)
+
+        helper_cd = ClockDomainsRenamer("helper")
+        self.submodules.filter_helper = helper_cd(thls.make(filters.helper, data_width=48))
+        self.submodules.filter_main = helper_cd(thls.make(filters.main, data_width=48))
+        self.comb += [
+            self.helper_dcxo.adpll_stb.eq(self.filter_helper.output_stb),
+            self.helper_dcxo.adpll.eq(self.filter_helper.output),
+            self.main_dcxo.adpll_stb.eq(self.filter_main.output_stb),
+            self.main_dcxo.adpll.eq(self.filter_main.output)
+        ]
diff --git a/artiq/gateware/drtio/wrpll/thls.py b/artiq/gateware/drtio/wrpll/thls.py
index 3f5aa6425..6d2509c63 100644
--- a/artiq/gateware/drtio/wrpll/thls.py
+++ b/artiq/gateware/drtio/wrpll/thls.py
@@ -589,6 +589,13 @@ class ProcessorImpl(Module):
         )
 
 
+def make(function, **kwargs):
+    proc = Processor(**kwargs)
+    cp = compile(proc, simple_test)
+    cp.dimension_processor()
+    return proc.implement(cp.encode(), cp.data)
+
+
 a = 0
 b = 0
 c = 0