forked from M-Labs/artiq
kc705: add SPI bus for memory card
This will be useful for SPI unit tests using a SD card as victim.
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298ceafd92
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@ -138,6 +138,13 @@ device_db = {
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"arguments": {"channel": 23}
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},
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"spi_mmc": {
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"type": "local",
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"module": "artiq.coredevice.spi",
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"class": "SPIMaster",
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"arguments": {"channel": 26}
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},
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"dac0": {
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"type": "local",
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"module": "artiq.coredevice.ad5360",
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@ -149,20 +156,20 @@ device_db = {
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"type": "local",
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"module": "artiq.coredevice.dds",
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"class": "DDSChannelAD9914",
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"arguments": {"bus_channel": 26, "channel": 0},
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"arguments": {"bus_channel": 27, "channel": 0},
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"comment": "Comments work in DDS panel as well"
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},
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"dds1": {
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"type": "local",
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"module": "artiq.coredevice.dds",
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"class": "DDSChannelAD9914",
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"arguments": {"bus_channel": 26, "channel": 1}
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"arguments": {"bus_channel": 27, "channel": 1}
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},
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"dds2": {
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"type": "local",
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"module": "artiq.coredevice.dds",
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"class": "DDSChannelAD9914",
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"arguments": {"bus_channel": 26, "channel": 2}
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"arguments": {"bus_channel": 27, "channel": 2}
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},
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"qc_q1_0": {
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@ -97,6 +97,16 @@ _ams101_dac = [
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)
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]
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_sdcard_spi_33 = [
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("sdcard_spi_33", 0,
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Subsignal("miso", Pins("AC20")),
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Subsignal("clk", Pins("AB23")),
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Subsignal("mosi", Pins("AB22")),
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Subsignal("cs_n", Pins("AC21")),
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IOStandard("LVCMOS33")
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)
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]
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class _NIST_Ions(MiniSoC, AMPSoC):
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mem_map = {
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@ -131,6 +141,7 @@ class _NIST_Ions(MiniSoC, AMPSoC):
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self.platform.add_extension(_sma33_io)
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self.platform.add_extension(_ams101_dac)
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self.platform.add_extension(_sdcard_spi_33)
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i2c = self.platform.request("i2c")
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self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
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@ -221,6 +232,11 @@ class NIST_CLOCK(_NIST_Ions):
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rtio_channels.append(rtio.Channel.from_phy(
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phy, ofifo_depth=128, ififo_depth=128))
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phy = spi.SPIMaster(platform.request("sdcard_spi_33", 0))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(
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phy, ofifo_depth=4, ififo_depth=4))
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phy = dds.AD9914(platform.request("dds"), 11, onehot=True)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy,
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@ -14,7 +14,7 @@ requirements:
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run:
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- python >=3.5.3,<3.6
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- setuptools 33.1.1
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- migen 0.5.dev py_112+gitd8b55c7
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- migen 0.5.dev py_117+gite826cb9
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- misoc 0.6.dev py_22+gite205c2ea
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- jesd204b 0.3
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- binutils-or1k-linux >=2.27
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@ -71,19 +71,21 @@ With the CLOCK hardware, the TTL lines are mapped as follows:
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The board has RTIO SPI buses mapped as follows:
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+--------------+-------------+-------------+-----------+------------+
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| RTIO channel | CS_N | MOSI | MISO | CLK |
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+==============+=============+=============+===========+============+
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| 22 | AMS101_CS_N | AMS101_MOSI | | AMS101_CLK |
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+--------------+-------------+-------------+-----------+------------+
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| 23 | SPI0_CS_N | SPI0_MOSI | SPI0_MISO | SPI0_CLK |
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+--------------+-------------+-------------+-----------+------------+
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| 24 | SPI1_CS_N | SPI1_MOSI | SPI1_MISO | SPI1_CLK |
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+--------------+-------------+-------------+-----------+------------+
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| 25 | SPI2_CS_N | SPI2_MOSI | SPI2_MISO | SPI2_CLK |
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+--------------+-------------+-------------+-----------+------------+
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+--------------+--------------+--------------+--------------+------------+
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| RTIO channel | CS_N | MOSI | MISO | CLK |
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+==============+==============+==============+==============+============+
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| 22 | AMS101_CS_N | AMS101_MOSI | | AMS101_CLK |
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+--------------+--------------+--------------+--------------+------------+
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| 23 | SPI0_CS_N | SPI0_MOSI | SPI0_MISO | SPI0_CLK |
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+--------------+--------------+--------------+--------------+------------+
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| 24 | SPI1_CS_N | SPI1_MOSI | SPI1_MISO | SPI1_CLK |
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+--------------+--------------+--------------+--------------+------------+
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| 25 | SPI2_CS_N | SPI2_MOSI | SPI2_MISO | SPI2_CLK |
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+--------------+--------------+--------------+--------------+------------+
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| 26 | MMC_SPI_CS_N | MMC_SPI_MOSI | MMC_SPI_MISO | MMC_SPI_CLK|
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+--------------+--------------+--------------+--------------+------------+
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The DDS bus is on channel 26.
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The DDS bus is on channel 27.
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NIST QC2
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