occheung/artiq
1
0
Fork 0
forked from M-Labs/artiq
Code Pull Requests Activity

rtio/core: fix syntax

Browse Source
This commit is contained in:
Robert Jördens 2016-03-09 17:10:21 +01:00
parent 03b53c3af9
commit 3f8e431de6
1 changed files with 2 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
artiq/gateware/rtio/core.py
View File

@ -133,11 +133,10 @@ class _OutputManager(Module):
# Note: replace may be asserted at the same time as collision
# when addresses are different. In that case, it is a collision.
self.sync.rsys += replace.eq(self.ev.timestamp == buf.timestamp)
self.sync.rsys += \
# Detect sequence errors on coarse timestamps only
# so that they are mutually exclusive with collision errors.
sequence_error.eq(self.ev.timestamp[fine_ts_width:]
< buf.timestamp[fine_ts_width:])
self.sync.rsys += sequence_error.eq(self.ev.timestamp[fine_ts_width:] <
buf.timestamp[fine_ts_width:])
if interface.enable_replace:
if hasattr(self.ev, "a"):
different_addresses = self.ev.a != buf.a