forked from M-Labs/artiq
flip logic of enable bit to bypass bit and update some comments
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@ -1094,7 +1094,7 @@ class PhaserChannel:
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raise ValueError("invalid profile index")
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addr = PHASER_ADDR_SERVO_CFG0 + self.index
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# enforce hold if the servo is bypassed
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data = (profile << 2) | (((hold | bypass) & 1) << 1) | (~bypass & 1)
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data = (profile << 2) | (((hold | bypass) & 1) << 1) | (bypass & 1)
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self.phaser.write8(addr, data)
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@kernel
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@ -1130,7 +1130,7 @@ class PhaserChannel:
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"""
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if (profile < 0) or (profile > 3):
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raise ValueError("invalid profile index")
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# 24 byte-sized ab registers per channel and 6 (2 bytes * 3 coefficients) registers per profile
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# 32 byte-sized data registers per channel and 8 (2 bytes * (3 coefficients + 1 offset)) registers per profile
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addr = PHASER_ADDR_SERVO_DATA_BASE + (8 * profile) + (self.index * 32)
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for data in [b0, b1, a1, offset]:
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self.phaser.write16(addr, data)
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