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phaser: tweak dac_setup

This commit is contained in:
Robert Jördens 2016-10-12 14:22:33 +02:00
parent 466d1e8304
commit 3f1d96b68d
1 changed files with 3 additions and 1 deletions
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4
artiq/examples/phaser/repository/dac_setup.py
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@ -37,11 +37,14 @@ class DACSetup(EnvExperiment):
self.core.break_realtime() self.core.break_realtime()
self.ad9154.jesd_enable(0) self.ad9154.jesd_enable(0)
self.ad9154.jesd_prbs(0) self.ad9154.jesd_prbs(0)
self.busywait_us(10000)
self.ad9154.init() self.ad9154.init()
self.dac_setup() self.dac_setup()
self.busywait_us(10000)
self.ad9154.jesd_enable(1) self.ad9154.jesd_enable(1)
while not self.ad9154.jesd_ready(): while not self.ad9154.jesd_ready():
pass pass
self.monitor()
if self.ad9154.dac_read(AD9154_CODEGRPSYNCFLG) != 0x0f: if self.ad9154.dac_read(AD9154_CODEGRPSYNCFLG) != 0x0f:
raise ValueError("no CODEGRPSYNCFLG") raise ValueError("no CODEGRPSYNCFLG")
self.core.break_realtime() self.core.break_realtime()
@ -53,7 +56,6 @@ class DACSetup(EnvExperiment):
raise ValueError("no GOODCHECKSUMFLG") raise ValueError("no GOODCHECKSUMFLG")
if self.ad9154.dac_read(AD9154_INITLANESYNCFLG) != 0x0f: if self.ad9154.dac_read(AD9154_INITLANESYNCFLG) != 0x0f:
raise ValueError("no INITLANESYNCFLG") raise ValueError("no INITLANESYNCFLG")
self.monitor()
@kernel @kernel
def busywait_us(self, t): def busywait_us(self, t):