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coredevice.ad9910: Fix phase tracking ref_time passing 

This is difficult to test without hardware mocks or some
form of phase readback, but the symptom was that e.g.
`self.dds.set(…, ref_time=now_mu() - 1)` would fail
periodically, that is, whenever bit 32 of the timestamp
would be set (which would be turned into the sign bit).

This is a fairly sinister issue, and is probably a compiler
bug of some sort (either accepts-invalid or wrong type inference).
This commit is contained in:
David Nadlinger 2019-01-12 00:43:15 +00:00
parent b3ef6e2253
commit 3e84ec2bf1
1 changed files with 4 additions and 2 deletions
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6
artiq/coredevice/ad9910.py
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@ -371,9 +371,11 @@ class AD9910:
self.set_cfr1(power_down=bits) self.set_cfr1(power_down=bits)
self.cpld.io_update.pulse(1*us) self.cpld.io_update.pulse(1*us)
# KLUDGE: ref_time default argument is explicitly marked int64() to avoid
# silent truncation of explicitly passed timestamps. (Compiler bug?)
@kernel @kernel
def set_mu(self, ftw, pow_=0, asf=0x3fff, phase_mode=_PHASE_MODE_DEFAULT, def set_mu(self, ftw, pow_=0, asf=0x3fff, phase_mode=_PHASE_MODE_DEFAULT,
ref_time=-1, profile=0): ref_time=int64(-1), profile=0):
"""Set profile 0 data in machine units. """Set profile 0 data in machine units.
This uses machine units (FTW, POW, ASF). The frequency tuning word This uses machine units (FTW, POW, ASF). The frequency tuning word
@ -514,7 +516,7 @@ class AD9910:
@kernel @kernel
def set(self, frequency, phase=0.0, amplitude=1.0, def set(self, frequency, phase=0.0, amplitude=1.0,
phase_mode=_PHASE_MODE_DEFAULT, ref_time=-1, profile=0): phase_mode=_PHASE_MODE_DEFAULT, ref_time=int64(-1), profile=0):
"""Set profile 0 data in SI units. """Set profile 0 data in SI units.
.. seealso:: :meth:`set_mu` .. seealso:: :meth:`set_mu`