From 3ad68f65c51348c834bf094058edd41c3d030ea4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Robert=20J=C3=B6rdens?= Date: Fri, 16 Nov 2018 14:56:26 +0000 Subject: [PATCH] urukul: make get_att_mu() not alter state MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Robert Jördens --- artiq/coredevice/urukul.py | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/artiq/coredevice/urukul.py b/artiq/coredevice/urukul.py index 8bb514c09..52221a018 100644 --- a/artiq/coredevice/urukul.py +++ b/artiq/coredevice/urukul.py @@ -309,15 +309,17 @@ class CPLD: def get_att_mu(self): """Return the digital step attenuator settings in machine units. - This method will also (as a side effect) write the attenuator - settings of all four channels. - :return: 32 bit attenuator settings """ - self.bus.set_config_mu(SPI_CONFIG | spi.SPI_END | spi.SPI_INPUT, 32, + self.bus.set_config_mu(SPI_CONFIG | spi.SPI_INPUT, 32, SPIT_ATT_RD, CS_ATT) - self.bus.write(self.att_reg) - return self.bus.read() + self.bus.write(0) # shift in zeros, shift out current value + self.bus.set_config_mu(SPI_CONFIG | spi.SPI_END, 32, + SPIT_ATT_WR, CS_ATT) + delay(10*us) + self.att_reg = self.bus.read() + self.bus.write(self.att_reg) # shift in current value again and latch + return self.att_reg @kernel def set_sync_div(self, div):