From 3a7819704a82ff2ace83d15c6bd4cbff27540806 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sun, 26 Apr 2020 16:04:32 +0800 Subject: [PATCH] rtio: support direct 64-bit now CSR in KernelInitiator --- artiq/gateware/rtio/cri.py | 34 ++++++++++++++++++++-------------- 1 file changed, 20 insertions(+), 14 deletions(-) diff --git a/artiq/gateware/rtio/cri.py b/artiq/gateware/rtio/cri.py index 0c135a5b4..0de13b8d1 100644 --- a/artiq/gateware/rtio/cri.py +++ b/artiq/gateware/rtio/cri.py @@ -60,11 +60,14 @@ class Interface(Record): class KernelInitiator(Module, AutoCSR): - def __init__(self, tsc, cri=None): + def __init__(self, tsc, cri=None, now64=False): self.target = CSRStorage(32) - # not using CSRStorage atomic_write feature here to make storage reset_less - self.now_hi = CSR(32) - self.now_lo = CSR(32) + if now64: + self.now = CSRStorage(64) + else: + # not using CSRStorage atomic_write feature here to make storage reset_less + self.now_hi = CSR(32) + self.now_lo = CSR(32) # Writing target clears o_data. This implements automatic # zero-extension of output event data by the gateware. When staging an @@ -87,16 +90,19 @@ class KernelInitiator(Module, AutoCSR): # # # - now_hi_backing = Signal(32) - now = Signal(64, reset_less=True) - self.sync += [ - If(self.now_hi.re, now_hi_backing.eq(self.now_hi.r)), - If(self.now_lo.re, now.eq(Cat(self.now_lo.r, now_hi_backing))) - ] - self.comb += [ - self.now_hi.w.eq(now[32:]), - self.now_lo.w.eq(now[:32]) - ] + if now64: + now = self.now.storage + else: + now = Signal(64, reset_less=True) + now_hi_backing = Signal(32) + self.sync += [ + If(self.now_hi.re, now_hi_backing.eq(self.now_hi.r)), + If(self.now_lo.re, now.eq(Cat(self.now_lo.r, now_hi_backing))) + ] + self.comb += [ + self.now_hi.w.eq(now[32:]), + self.now_lo.w.eq(now[:32]) + ] self.comb += [ self.cri.cmd.eq(commands["nop"]),