From 3931d8097bdd9e619583bf56a318efee8f2d4e39 Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Thu, 1 Dec 2016 16:43:46 +0800
Subject: [PATCH] rtio: fix DMA TimeOffset stream.connect

---
 artiq/gateware/rtio/dma.py | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/artiq/gateware/rtio/dma.py b/artiq/gateware/rtio/dma.py
index 210a352d5..244e0be5c 100644
--- a/artiq/gateware/rtio/dma.py
+++ b/artiq/gateware/rtio/dma.py
@@ -194,8 +194,8 @@ class TimeOffset(Module, AutoCSR):
         pipe_ce = Signal()
         self.sync += \
             If(pipe_ce,
-                self.source.payload.connect(self.sink.payload,
-                                            leave_out={"timestamp"}),
+                self.sink.payload.connect(self.source.payload,
+                                          leave_out={"timestamp"}),
                 self.source.payload.timestamp.eq(self.sink.payload.timestamp
                                                  + self.time_offset.storage),
                 self.source.stb.eq(self.sink.stb)