From 3809ac5470961092cfbd8d28250ef38b9c8462d1 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Robert=20J=C3=B6rdens?= <rj@quartiq.de>
Date: Fri, 2 Sep 2022 19:47:06 +0000
Subject: [PATCH] fix type, clean clear

---
 artiq/coredevice/phaser.py        | 1 +
 artiq/gateware/rtio/phy/phaser.py | 5 ++++-
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/artiq/coredevice/phaser.py b/artiq/coredevice/phaser.py
index b53782a3a..386c1897a 100644
--- a/artiq/coredevice/phaser.py
+++ b/artiq/coredevice/phaser.py
@@ -1351,6 +1351,7 @@ class Miqro:
                 idx = 0
             data[word] |= (profiles[i] & 0x1f) << idx
             idx += 5
+        delay_mu(-8*word)
         while word >= 0:
             rtio_output(self.base_addr + word, data[word])
             delay_mu(8)
diff --git a/artiq/gateware/rtio/phy/phaser.py b/artiq/gateware/rtio/phy/phaser.py
index 078984477..1a1ced03d 100644
--- a/artiq/gateware/rtio/phy/phaser.py
+++ b/artiq/gateware/rtio/phy/phaser.py
@@ -111,6 +111,9 @@ class MiqroChannel(Module):
             If(self.ack,
                 dt[1:].eq(0),
                 stb.eq(0),
+                If(stb,
+                    [r.eq(0) for r in regs],
+                ),
             ),
             If(self.rtlink.o.stb,
                 Array(regs)[self.rtlink.o.address].eq(self.rtlink.o.data),
@@ -159,7 +162,7 @@ class Miqro(Module):
 
         re_dly = Signal(3)  # stage, send, respond
         self.sync.rtio += [
-            header.type.eq(1),  # body type is miqro pulse data
+            header.type.eq(3),  # body type is miqro pulse data
             If(self.serializer.stb,
                 header.we.eq(0),
                 re_dly.eq(re_dly[1:]),