From 3802c7badb08417843e4a9786a665f6d9720e12f Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 27 Apr 2018 13:20:20 +0200 Subject: [PATCH] firmware/ad9154: add sysref scan/conf for jesd sc1 --- artiq/firmware/libboard_artiq/ad9154.rs | 40 ++++++++++++++++++++ artiq/firmware/libboard_artiq/hmc830_7043.rs | 16 +++++++- 2 files changed, 55 insertions(+), 1 deletion(-) diff --git a/artiq/firmware/libboard_artiq/ad9154.rs b/artiq/firmware/libboard_artiq/ad9154.rs index 9cd40b169..2f9bbd86c 100644 --- a/artiq/firmware/libboard_artiq/ad9154.rs +++ b/artiq/firmware/libboard_artiq/ad9154.rs @@ -1,5 +1,6 @@ use board::{csr, clock}; use ad9154_reg; +use hmc830_7043::{hmc7043}; fn spi_setup(dacno: u8) { unsafe { @@ -607,6 +608,44 @@ fn dac_cfg_retry(dacno: u8) -> Result<(), &'static str> { dac_cfg(dacno) } +fn dac_sysref_cfg(dacno: u8) { + let mut sync_error: u16 = 0; + let mut sync_error_last: u16 = 0; + let mut cphase_min_found: bool = false; + let mut cphase_min: u8 = 0; + let mut cphase_max_found: bool = false; + let mut cphase_max: u8 = 0; + let mut cphase_opt: u8 = 0; + + info!("AD9154-{} SYSREF scan/conf...", dacno); + for cphase in 0..32 { + hmc7043::cfg_dac_sysref(dacno, 0, cphase); + clock::spin_us(10000); + spi_setup(dacno); + sync_error = ((read(ad9154_reg::SYNC_CURRERR_L) as u16) | + ((read(ad9154_reg::SYNC_CURRERR_H) as u16) << 8)) + & 0x1ff; + info!(" cphase: {}, sync error: {}", cphase, sync_error); + if sync_error != 0 { + if cphase_min_found { + if sync_error != sync_error_last { + cphase_max_found = true; + cphase_max = cphase - 1; + break; + } + } else { + cphase_min_found = true; + cphase_min = cphase; + } + } + sync_error_last = sync_error; + } + + cphase_opt = cphase_min + (cphase_max-cphase_min)/2; + info!(" cphase min: {}, cphase max: {}, cphase opt: {}", cphase_min, cphase_max, cphase_opt); + hmc7043::cfg_dac_sysref(dacno, 0, cphase_opt); +} + pub fn init() -> Result<(), &'static str> { // Release the JESD clock domain reset late, as we need to // set up clock chips before. @@ -617,6 +656,7 @@ pub fn init() -> Result<(), &'static str> { debug!("setting up AD9154-{} DAC...", dacno); dac_cfg_retry(dacno)?; dac_prbs(dacno)?; + dac_sysref_cfg(dacno); dac_cfg_retry(dacno)?; } diff --git a/artiq/firmware/libboard_artiq/hmc830_7043.rs b/artiq/firmware/libboard_artiq/hmc830_7043.rs index 44bf0f967..b1e5d9201 100644 --- a/artiq/firmware/libboard_artiq/hmc830_7043.rs +++ b/artiq/firmware/libboard_artiq/hmc830_7043.rs @@ -124,7 +124,7 @@ mod hmc830 { } } -mod hmc7043 { +pub mod hmc7043 { use board::csr; // To do: check which output channels we actually need @@ -249,6 +249,20 @@ mod hmc7043 { Ok(()) } + + pub fn cfg_dac_sysref(dacno: u8, aphase: u8, cphase: u8) { + spi_setup(); + if dacno == 0 { + write(0x00D5, aphase); + write(0x00D6, cphase); + } else if dacno == 1 { + write(0x00E9, aphase); + write(0x00EA, cphase); + } else { + unimplemented!(); + } + } + } pub fn init() -> Result<(), &'static str> {