From 37f9c0b10c47a826b88bd6ff6cb9551f80e49e34 Mon Sep 17 00:00:00 2001
From: Robert Jordens <rj@m-labs.hk>
Date: Thu, 28 Dec 2017 16:49:35 +0100
Subject: [PATCH] spi: register clk

following m-labs/misoc#65
https://github.com/m-labs/misoc/commit/1dc68b0d0b19ecb35878d345034b2f0853a10bb8
---
 artiq/gateware/spi.py | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/artiq/gateware/spi.py b/artiq/gateware/spi.py
index 182a934f5..59cc64dbe 100644
--- a/artiq/gateware/spi.py
+++ b/artiq/gateware/spi.py
@@ -203,7 +203,11 @@ class SPIMaster(Module):
             mosi_oe.eq(
                 ~config.offline & spi.cs &
                 (spi.oe | ~config.half_duplex)),
-            clk.eq((spi.cg.clk & spi.cs) ^ config.clk_polarity)
+        ]
+        self.sync += [
+            If(spi.cg.ce & spi.cg.edge,
+                clk.eq((~spi.cg.clk & spi.cs_next) ^ config.clk_polarity)
+            )
         ]
 
         if pads_n is None: