From 37d0a5dc19bde90c5521c13cc942a138f270fb8b Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Wed, 16 Oct 2019 18:48:20 +0800 Subject: [PATCH] rtio/ttl: expose OE --- artiq/gateware/rtio/phy/ttl_serdes_generic.py | 8 ++++++-- artiq/gateware/rtio/phy/ttl_simple.py | 8 ++++++-- 2 files changed, 12 insertions(+), 4 deletions(-) diff --git a/artiq/gateware/rtio/phy/ttl_serdes_generic.py b/artiq/gateware/rtio/phy/ttl_serdes_generic.py index e770052c6..5e03297fa 100644 --- a/artiq/gateware/rtio/phy/ttl_serdes_generic.py +++ b/artiq/gateware/rtio/phy/ttl_serdes_generic.py @@ -67,6 +67,8 @@ class InOut(Module): override_oe = Signal() self.overrides = [override_en, override_o, override_oe] + # Output enable, for interfacing to external buffers. + self.oe = Signal() # LSB of the input state (for edge detection; arbitrary choice, support for # short pulses will need a more involved solution). self.input_state = Signal() @@ -82,15 +84,17 @@ class InOut(Module): override_en=override_en, override_o=override_o) oe_k = Signal() + self.oe.attr.add("no_retiming") self.sync.rio_phy += [ If(self.rtlink.o.stb & (self.rtlink.o.address == 1), oe_k.eq(self.rtlink.o.data[0])), If(override_en, - serdes.oe.eq(override_oe) + self.oe.eq(override_oe) ).Else( - serdes.oe.eq(oe_k) + self.oe.eq(oe_k) ) ] + self.comb += serdes.oe.eq(self.oe) # Input sensitivity = Signal(2) diff --git a/artiq/gateware/rtio/phy/ttl_simple.py b/artiq/gateware/rtio/phy/ttl_simple.py index aef84cb69..4484ce3af 100644 --- a/artiq/gateware/rtio/phy/ttl_simple.py +++ b/artiq/gateware/rtio/phy/ttl_simple.py @@ -90,6 +90,8 @@ class InOut(Module): self.overrides = [override_en, override_o, override_oe] self.probes = [] + # Output enable, for interfacing to external buffers. + self.oe = Signal() # Registered copy of the input state, in the rio_phy clock domain. self.input_state = Signal() @@ -101,6 +103,7 @@ class InOut(Module): o_k = Signal() oe_k = Signal() + self.oe.attr.add("no_retiming") self.sync.rio_phy += [ If(self.rtlink.o.stb, If(self.rtlink.o.address == 0, o_k.eq(self.rtlink.o.data[0])), @@ -108,12 +111,13 @@ class InOut(Module): ), If(override_en, ts.o.eq(override_o), - ts.oe.eq(override_oe) + self.oe.eq(override_oe) ).Else( ts.o.eq(o_k), - ts.oe.eq(oe_k) + self.oe.eq(oe_k) ) ] + self.comb += ts.oe.eq(self.oe) sample = Signal() self.sync.rio += [ sample.eq(0),