From 3638a966e14848c5861e2331ca7f8066cf874c01 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sat, 21 Jul 2018 13:26:13 +0800 Subject: [PATCH] kasli: add false path between RTIO and CL clocks --- artiq/gateware/targets/kasli.py | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/artiq/gateware/targets/kasli.py b/artiq/gateware/targets/kasli.py index ab0abb2d2..b59b5c330 100755 --- a/artiq/gateware/targets/kasli.py +++ b/artiq/gateware/targets/kasli.py @@ -299,6 +299,8 @@ class MITLL(_StandaloneBase): self.add_rtio(self.rtio_channels) self.config["HAS_GRABBER"] = None self.add_csr_group("grabber", self.grabber_csr_group) + self.platform.add_false_path_constraints( + self.rtio_crg.cd_rtio.clk, self.grabber0.deserializer.cd_cl.clk) class USTC(_StandaloneBase): @@ -338,6 +340,8 @@ class USTC(_StandaloneBase): self.add_rtio(self.rtio_channels) self.config["HAS_GRABBER"] = None self.add_csr_group("grabber", self.grabber_csr_group) + self.platform.add_false_path_constraints( + self.rtio_crg.cd_rtio.clk, self.grabber0.deserializer.cd_cl.clk) class Tsinghua(_StandaloneBase): @@ -374,6 +378,8 @@ class Tsinghua(_StandaloneBase): self.add_rtio(self.rtio_channels) self.config["HAS_GRABBER"] = None self.add_csr_group("grabber", self.grabber_csr_group) + self.platform.add_false_path_constraints( + self.rtio_crg.cd_rtio.clk, self.grabber0.deserializer.cd_cl.clk) class WIPM(_StandaloneBase): @@ -543,6 +549,8 @@ class LUH(_StandaloneBase): self.add_rtio(self.rtio_channels) self.config["HAS_GRABBER"] = None self.add_csr_group("grabber", self.grabber_csr_group) + self.platform.add_false_path_constraints( + self.rtio_crg.cd_rtio.clk, self.grabber0.deserializer.cd_cl.clk) class Tester(_StandaloneBase):