forked from M-Labs/artiq
gateware/targets/sayma_amc_standalone/rtm: use new serwb modules
This commit is contained in:
Florent Kermarrec
parent
41d57d64f6
commit
32ca51faee
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@ -58,59 +58,32 @@ class SaymaAMCStandalone(MiniSoC, AMPSoC):
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# AMC/RTM serwb
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# TODO: cleanup (same comments as in sayma_rtm.py)
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serwb_pll = serwb.kusphy.KUSSerdesPLL(self.clk_freq, 1.25e9, vco_div=2)
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# serwb SERDES
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serwb_pll = serwb.phy.SERWBPLL(125e6, 1.25e9, vco_div=1)
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self.comb += serwb_pll.refclk.eq(self.crg.cd_sys.clk)
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self.submodules += serwb_pll
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serwb_pads = platform.request("amc_rtm_serwb")
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serwb_serdes = serwb.kusphy.KUSSerdes(serwb_pll, serwb_pads, mode="master")
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self.submodules += serwb_serdes
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serwb_init = serwb.phy.SerdesMasterInit(serwb_serdes, taps=512)
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self.submodules += serwb_init
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self.submodules.serwb_control = serwb.phy.SerdesControl(serwb_init, mode="master")
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self.csr_devices.append("serwb_control")
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serwb_phy = serwb.phy.SERWBPHY(platform.device, serwb_pll, serwb_pads, mode="slave")
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self.submodules.serwb_phy = serwb_phy
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self.csr_devices.append("serwb_phy")
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serwb_serdes.cd_serdes.clk.attr.add("keep")
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serwb_serdes.cd_serdes_20x.clk.attr.add("keep")
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serwb_serdes.cd_serdes_5x.clk.attr.add("keep")
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platform.add_period_constraint(serwb_serdes.cd_serdes.clk, 32.0),
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platform.add_period_constraint(serwb_serdes.cd_serdes_20x.clk, 1.6),
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platform.add_period_constraint(serwb_serdes.cd_serdes_5x.clk, 6.4)
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serwb_phy.serdes.cd_serdes.clk.attr.add("keep")
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serwb_phy.serdes.cd_serdes_20x.clk.attr.add("keep")
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serwb_phy.serdes.cd_serdes_5x.clk.attr.add("keep")
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platform.add_period_constraint(serwb_phy.serdes.cd_serdes.clk, 32.0),
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platform.add_period_constraint(serwb_phy.serdes.cd_serdes_20x.clk, 1.6),
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platform.add_period_constraint(serwb_phy.serdes.cd_serdes_5x.clk, 6.4)
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk,
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serwb_serdes.cd_serdes.clk,
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serwb_serdes.cd_serdes_5x.clk)
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serwb_phy.serdes.cd_serdes.clk,
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serwb_phy.serdes.cd_serdes_5x.clk)
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serwb_depacketizer = serwb.packet.Depacketizer(self.clk_freq)
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serwb_packetizer = serwb.packet.Packetizer()
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self.submodules += serwb_depacketizer, serwb_packetizer
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serwb_etherbone = serwb.etherbone.Etherbone(mode="slave")
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self.submodules += serwb_etherbone
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self.comb += serwb_etherbone.wishbone.ready.eq(serwb_init.ready)
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serwb_tx_cdc = ClockDomainsRenamer({"write": "sys", "read": "serdes"})(
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stream.AsyncFIFO([("data", 32)], 8))
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self.submodules += serwb_tx_cdc
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serwb_rx_cdc = ClockDomainsRenamer({"write": "serdes", "read": "sys"})(
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stream.AsyncFIFO([("data", 32)], 8))
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self.submodules += serwb_rx_cdc
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self.comb += [
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# core <--> etherbone
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serwb_depacketizer.source.connect(serwb_etherbone.sink),
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serwb_etherbone.source.connect(serwb_packetizer.sink),
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# core --> serdes
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serwb_packetizer.source.connect(serwb_tx_cdc.sink),
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If(serwb_tx_cdc.source.stb & serwb_init.ready,
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serwb_serdes.tx_data.eq(serwb_tx_cdc.source.data)
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),
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serwb_tx_cdc.source.ack.eq(serwb_init.ready),
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# serdes --> core
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serwb_rx_cdc.sink.stb.eq(serwb_init.ready),
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serwb_rx_cdc.sink.data.eq(serwb_serdes.rx_data),
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serwb_rx_cdc.source.connect(serwb_depacketizer.sink),
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]
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self.add_wb_slave(self.mem_map["serwb"], 8192, serwb_etherbone.wishbone.bus)
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# serwb slave
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serwb_core = serwb.core.SERWBCore(serwb_phy, int(self.clk_freq), mode="slave")
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self.submodules += serwb_core
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self.add_wb_slave(self.mem_map["serwb"], 8192, serwb_core.etherbone.wishbone.bus)
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# RTIO
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rtio_channels = []
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@ -98,62 +98,32 @@ class SaymaRTM(Module):
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csr_devices.append("converter_spi")
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self.comb += platform.request("hmc7043_reset").eq(0)
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# TODO: push all those serwb bits into library modules
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# maybe keep only 3 user-visible modules: serwb PLL, serwb PHY, and serwb core
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# TODO: after this is done, stop exposing internal modules in serwb/__init__.py
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# TODO: avoid having a "serdes" clock domain at the top level, rename to "serwb_serdes" or similar.
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# TODO: the above also applies to sayma_amc_standalone.py.
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# serwb SERDES
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serwb_pll = serwb.s7phy.S7SerdesPLL(125e6, 1.25e9, vco_div=1)
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serwb_pll = serwb.phy.SERWBPLL(125e6, 1.25e9, vco_div=1)
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self.submodules += serwb_pll
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serwb_serdes = serwb.s7phy.S7Serdes(serwb_pll, platform.request("amc_rtm_serwb"), mode="slave")
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self.submodules += serwb_serdes
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serwb_init = serwb.phy.SerdesSlaveInit(serwb_serdes, taps=32)
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self.submodules += serwb_init
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self.comb += self.crg.reset.eq(serwb_init.reset)
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serwb_pads = platform.request("amc_rtm_serwb")
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serwb_phy = serwb.phy.SERWBPHY(platform.device, serwb_pll, serwb_pads, mode="slave")
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self.submodules.serwb_phy = serwb_phy
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self.comb += self.crg.reset.eq(serwb_phy.init.reset)
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serwb_serdes.cd_serdes.clk.attr.add("keep")
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serwb_serdes.cd_serdes_20x.clk.attr.add("keep")
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serwb_serdes.cd_serdes_5x.clk.attr.add("keep")
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platform.add_period_constraint(serwb_serdes.cd_serdes.clk, 32.0),
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platform.add_period_constraint(serwb_serdes.cd_serdes_20x.clk, 1.6),
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platform.add_period_constraint(serwb_serdes.cd_serdes_5x.clk, 6.4)
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serwb_phy.serdes.cd_serdes.clk.attr.add("keep")
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serwb_phy.serdes.cd_serdes_20x.clk.attr.add("keep")
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serwb_phy.serdes.cd_serdes_5x.clk.attr.add("keep")
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platform.add_period_constraint(serwb_phy.serdes.cd_serdes.clk, 32.0),
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platform.add_period_constraint(serwb_phy.serdes.cd_serdes_20x.clk, 1.6),
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platform.add_period_constraint(serwb_phy.serdes.cd_serdes_5x.clk, 6.4)
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk,
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serwb_serdes.cd_serdes.clk,
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serwb_serdes.cd_serdes_5x.clk)
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serwb_phy.serdes.cd_serdes.clk,
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serwb_phy.serdes.cd_serdes_5x.clk)
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# serwb master
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serwb_depacketizer = serwb.packet.Depacketizer(int(clk_freq))
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serwb_packetizer = serwb.packet.Packetizer()
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self.submodules += serwb_depacketizer, serwb_packetizer
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serwb_etherbone = serwb.etherbone.Etherbone(mode="master")
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self.submodules += serwb_etherbone
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serwb_tx_cdc = ClockDomainsRenamer({"write": "sys", "read": "serdes"})(
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stream.AsyncFIFO([("data", 32)], 8))
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self.submodules += serwb_tx_cdc
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serwb_rx_cdc = ClockDomainsRenamer({"write": "serdes", "read": "sys"})(
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stream.AsyncFIFO([("data", 32)], 8))
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self.submodules += serwb_rx_cdc
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self.comb += [
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# core <--> etherbone
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serwb_depacketizer.source.connect(serwb_etherbone.sink),
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serwb_etherbone.source.connect(serwb_packetizer.sink),
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# core --> serdes
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serwb_packetizer.source.connect(serwb_tx_cdc.sink),
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If(serwb_tx_cdc.source.stb & serwb_init.ready,
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serwb_serdes.tx_data.eq(serwb_tx_cdc.source.data)
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),
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serwb_tx_cdc.source.ack.eq(serwb_init.ready),
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# serdes --> core
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serwb_rx_cdc.sink.stb.eq(serwb_init.ready),
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serwb_rx_cdc.sink.data.eq(serwb_serdes.rx_data),
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serwb_rx_cdc.source.connect(serwb_depacketizer.sink),
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]
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serwb_core = serwb.core.SERWBCore(serwb_phy, int(clk_freq), mode="master")
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self.submodules += serwb_core
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# process CSR devices and connect them to serwb
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self.csr_regions = []
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@ -169,7 +139,7 @@ class SaymaRTM(Module):
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wb_slaves.add(origin, CSR_RANGE_SIZE, bank.bus)
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self.csr_regions.append((name, origin, 32, csrs))
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self.submodules += wishbone.Decoder(serwb_etherbone.wishbone.bus,
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self.submodules += wishbone.Decoder(serwb_core.etherbone.wishbone.bus,
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wb_slaves.get_interconnect_slaves(),
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register=True)
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