forked from M-Labs/artiq
kc705: remove Zotino and Urukul
* use Kasli instead for using EEMs * code required outdated VHDCI adapter 1.0
This commit is contained in:
parent
13984385a8
commit
3168b193e6
|
|
@ -119,34 +119,6 @@ device_db = {
|
||||||
"arguments": {"channel": 26}
|
"arguments": {"channel": 26}
|
||||||
},
|
},
|
||||||
|
|
||||||
# FMC DIO used to connect to Zotino
|
|
||||||
"fmcdio_dirctl_clk": {
|
|
||||||
"type": "local",
|
|
||||||
"module": "artiq.coredevice.ttl",
|
|
||||||
"class": "TTLOut",
|
|
||||||
"arguments": {"channel": 27}
|
|
||||||
},
|
|
||||||
"fmcdio_dirctl_ser": {
|
|
||||||
"type": "local",
|
|
||||||
"module": "artiq.coredevice.ttl",
|
|
||||||
"class": "TTLOut",
|
|
||||||
"arguments": {"channel": 28}
|
|
||||||
},
|
|
||||||
"fmcdio_dirctl_latch": {
|
|
||||||
"type": "local",
|
|
||||||
"module": "artiq.coredevice.ttl",
|
|
||||||
"class": "TTLOut",
|
|
||||||
"arguments": {"channel": 29}
|
|
||||||
},
|
|
||||||
"fmcdio_dirctl": {
|
|
||||||
"type": "local",
|
|
||||||
"module": "artiq.coredevice.shiftreg",
|
|
||||||
"class": "ShiftReg",
|
|
||||||
"arguments": {"clk": "fmcdio_dirctl_clk",
|
|
||||||
"ser": "fmcdio_dirctl_ser",
|
|
||||||
"latch": "fmcdio_dirctl_latch"}
|
|
||||||
},
|
|
||||||
|
|
||||||
# DAC
|
# DAC
|
||||||
"spi_ams101": {
|
"spi_ams101": {
|
||||||
"type": "local",
|
"type": "local",
|
||||||
|
|
@ -160,184 +132,26 @@ device_db = {
|
||||||
"class": "TTLOut",
|
"class": "TTLOut",
|
||||||
"arguments": {"channel": 20}
|
"arguments": {"channel": 20}
|
||||||
},
|
},
|
||||||
"spi_zotino": {
|
|
||||||
"type": "local",
|
|
||||||
"module": "artiq.coredevice.spi2",
|
|
||||||
"class": "SPIMaster",
|
|
||||||
"arguments": {"channel": 30}
|
|
||||||
},
|
|
||||||
"ttl_zotino_ldac": {
|
|
||||||
"type": "local",
|
|
||||||
"module": "artiq.coredevice.ttl",
|
|
||||||
"class": "TTLOut",
|
|
||||||
"arguments": {"channel": 31}
|
|
||||||
},
|
|
||||||
"dac_zotino": {
|
|
||||||
"type": "local",
|
|
||||||
"module": "artiq.coredevice.zotino",
|
|
||||||
"class": "Zotino",
|
|
||||||
"arguments": {
|
|
||||||
"spi_device": "spi_zotino",
|
|
||||||
"ldac_device": "ttl_zotino_ldac",
|
|
||||||
"div_write": 30,
|
|
||||||
"div_read": 40
|
|
||||||
}
|
|
||||||
},
|
|
||||||
|
|
||||||
"spi_urukul": {
|
|
||||||
"type": "local",
|
|
||||||
"module": "artiq.coredevice.spi2",
|
|
||||||
"class": "SPIMaster",
|
|
||||||
"arguments": {"channel": 32}
|
|
||||||
},
|
|
||||||
"ttl_urukul_io_update": {
|
|
||||||
"type": "local",
|
|
||||||
"module": "artiq.coredevice.ttl",
|
|
||||||
"class": "TTLOut",
|
|
||||||
"arguments": {"channel": 33}
|
|
||||||
},
|
|
||||||
"ttl_urukul_sw0": {
|
|
||||||
"type": "local",
|
|
||||||
"module": "artiq.coredevice.ttl",
|
|
||||||
"class": "TTLOut",
|
|
||||||
"arguments": {"channel": 35}
|
|
||||||
},
|
|
||||||
"ttl_urukul_sw1": {
|
|
||||||
"type": "local",
|
|
||||||
"module": "artiq.coredevice.ttl",
|
|
||||||
"class": "TTLOut",
|
|
||||||
"arguments": {"channel": 36}
|
|
||||||
},
|
|
||||||
"ttl_urukul_sw2": {
|
|
||||||
"type": "local",
|
|
||||||
"module": "artiq.coredevice.ttl",
|
|
||||||
"class": "TTLOut",
|
|
||||||
"arguments": {"channel": 37}
|
|
||||||
},
|
|
||||||
"ttl_urukul_sw3": {
|
|
||||||
"type": "local",
|
|
||||||
"module": "artiq.coredevice.ttl",
|
|
||||||
"class": "TTLOut",
|
|
||||||
"arguments": {"channel": 38}
|
|
||||||
},
|
|
||||||
"urukul_cpld": {
|
|
||||||
"type": "local",
|
|
||||||
"module": "artiq.coredevice.urukul",
|
|
||||||
"class": "CPLD",
|
|
||||||
"arguments": {
|
|
||||||
"spi_device": "spi_urukul",
|
|
||||||
"io_update_device": "ttl_urukul_io_update",
|
|
||||||
"refclk": 100e6
|
|
||||||
}
|
|
||||||
},
|
|
||||||
"urukul_ch0a": {
|
|
||||||
"type": "local",
|
|
||||||
"module": "artiq.coredevice.ad9912",
|
|
||||||
"class": "AD9912",
|
|
||||||
"arguments": {
|
|
||||||
"pll_n": 10,
|
|
||||||
"chip_select": 4,
|
|
||||||
"cpld_device": "urukul_cpld",
|
|
||||||
"sw_device": "ttl_urukul_sw0"
|
|
||||||
}
|
|
||||||
},
|
|
||||||
"urukul_ch1a": {
|
|
||||||
"type": "local",
|
|
||||||
"module": "artiq.coredevice.ad9912",
|
|
||||||
"class": "AD9912",
|
|
||||||
"arguments": {
|
|
||||||
"pll_n": 10,
|
|
||||||
"chip_select": 5,
|
|
||||||
"cpld_device": "urukul_cpld",
|
|
||||||
"sw_device": "ttl_urukul_sw1"
|
|
||||||
}
|
|
||||||
},
|
|
||||||
"urukul_ch2a": {
|
|
||||||
"type": "local",
|
|
||||||
"module": "artiq.coredevice.ad9912",
|
|
||||||
"class": "AD9912",
|
|
||||||
"arguments": {
|
|
||||||
"pll_n": 10,
|
|
||||||
"chip_select": 6,
|
|
||||||
"cpld_device": "urukul_cpld",
|
|
||||||
"sw_device": "ttl_urukul_sw2"
|
|
||||||
}
|
|
||||||
},
|
|
||||||
"urukul_ch3a": {
|
|
||||||
"type": "local",
|
|
||||||
"module": "artiq.coredevice.ad9912",
|
|
||||||
"class": "AD9912",
|
|
||||||
"arguments": {
|
|
||||||
"pll_n": 10,
|
|
||||||
"chip_select": 7,
|
|
||||||
"cpld_device": "urukul_cpld",
|
|
||||||
"sw_device": "ttl_urukul_sw3"
|
|
||||||
}
|
|
||||||
},
|
|
||||||
"urukul_ch0b": {
|
|
||||||
"type": "local",
|
|
||||||
"module": "artiq.coredevice.ad9910",
|
|
||||||
"class": "AD9910",
|
|
||||||
"arguments": {
|
|
||||||
"pll_n": 40,
|
|
||||||
"chip_select": 4,
|
|
||||||
"cpld_device": "urukul_cpld",
|
|
||||||
"sw_device": "ttl_urukul_sw0"
|
|
||||||
}
|
|
||||||
},
|
|
||||||
"urukul_ch1b": {
|
|
||||||
"type": "local",
|
|
||||||
"module": "artiq.coredevice.ad9910",
|
|
||||||
"class": "AD9910",
|
|
||||||
"arguments": {
|
|
||||||
"pll_n": 40,
|
|
||||||
"chip_select": 5,
|
|
||||||
"cpld_device": "urukul_cpld",
|
|
||||||
"sw_device": "ttl_urukul_sw1"
|
|
||||||
}
|
|
||||||
},
|
|
||||||
"urukul_ch2b": {
|
|
||||||
"type": "local",
|
|
||||||
"module": "artiq.coredevice.ad9910",
|
|
||||||
"class": "AD9910",
|
|
||||||
"arguments": {
|
|
||||||
"pll_n": 40,
|
|
||||||
"chip_select": 6,
|
|
||||||
"cpld_device": "urukul_cpld",
|
|
||||||
"sw_device": "ttl_urukul_sw2"
|
|
||||||
}
|
|
||||||
},
|
|
||||||
"urukul_ch3b": {
|
|
||||||
"type": "local",
|
|
||||||
"module": "artiq.coredevice.ad9910",
|
|
||||||
"class": "AD9910",
|
|
||||||
"arguments": {
|
|
||||||
"pll_n": 40,
|
|
||||||
"chip_select": 7,
|
|
||||||
"cpld_device": "urukul_cpld",
|
|
||||||
"sw_device": "ttl_urukul_sw3"
|
|
||||||
}
|
|
||||||
},
|
|
||||||
|
|
||||||
# AD9914 DDS
|
# AD9914 DDS
|
||||||
"dds0": {
|
"dds0": {
|
||||||
"type": "local",
|
"type": "local",
|
||||||
"module": "artiq.coredevice.ad9914",
|
"module": "artiq.coredevice.ad9914",
|
||||||
"class": "AD9914",
|
"class": "AD9914",
|
||||||
"arguments": {"sysclk": 3e9, "bus_channel": 39, "channel": 0},
|
"arguments": {"sysclk": 3e9, "bus_channel": 27, "channel": 0},
|
||||||
"comment": "Comments work in DDS panel as well"
|
"comment": "Comments work in DDS panel as well"
|
||||||
},
|
},
|
||||||
"dds1": {
|
"dds1": {
|
||||||
"type": "local",
|
"type": "local",
|
||||||
"module": "artiq.coredevice.ad9914",
|
"module": "artiq.coredevice.ad9914",
|
||||||
"class": "AD9914",
|
"class": "AD9914",
|
||||||
"arguments": {"sysclk": 3e9, "bus_channel": 39, "channel": 1}
|
"arguments": {"sysclk": 3e9, "bus_channel": 27, "channel": 1}
|
||||||
},
|
},
|
||||||
"dds2": {
|
"dds2": {
|
||||||
"type": "local",
|
"type": "local",
|
||||||
"module": "artiq.coredevice.ad9914",
|
"module": "artiq.coredevice.ad9914",
|
||||||
"class": "AD9914",
|
"class": "AD9914",
|
||||||
"arguments": {"sysclk": 3e9, "bus_channel": 39, "channel": 2}
|
"arguments": {"sysclk": 3e9, "bus_channel": 27, "channel": 2}
|
||||||
},
|
},
|
||||||
|
|
||||||
# Aliases
|
# Aliases
|
||||||
|
|
|
||||||
|
|
@ -16,8 +16,7 @@ from misoc.integration.builder import builder_args, builder_argdict
|
||||||
|
|
||||||
from artiq.gateware.amp import AMPSoC
|
from artiq.gateware.amp import AMPSoC
|
||||||
from artiq.gateware import rtio, nist_clock, nist_qc2
|
from artiq.gateware import rtio, nist_clock, nist_qc2
|
||||||
from artiq.gateware.rtio.phy import (ttl_simple, ttl_serdes_7series,
|
from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series, dds, spi2
|
||||||
dds, spi2, ad53xx_monitor)
|
|
||||||
from artiq.build_soc import *
|
from artiq.build_soc import *
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -109,99 +108,6 @@ _sdcard_spi_33 = [
|
||||||
)
|
)
|
||||||
]
|
]
|
||||||
|
|
||||||
_zotino = [
|
|
||||||
("fmcdio_dirctl", 0,
|
|
||||||
Subsignal("clk", Pins("HPC:LA32_N")),
|
|
||||||
Subsignal("ser", Pins("HPC:LA33_P")),
|
|
||||||
Subsignal("latch", Pins("HPC:LA32_P")),
|
|
||||||
IOStandard("LVCMOS25")
|
|
||||||
),
|
|
||||||
("zotino_spi_p", 0,
|
|
||||||
Subsignal("clk", Pins("HPC:LA08_P")),
|
|
||||||
Subsignal("mosi", Pins("HPC:LA09_P")),
|
|
||||||
Subsignal("miso", Pins("HPC:LA10_P")),
|
|
||||||
Subsignal("cs_n", Pins("HPC:LA11_P")),
|
|
||||||
IOStandard("LVDS_25")
|
|
||||||
),
|
|
||||||
("zotino_spi_n", 0,
|
|
||||||
Subsignal("clk", Pins("HPC:LA08_N")),
|
|
||||||
Subsignal("mosi", Pins("HPC:LA09_N")),
|
|
||||||
Subsignal("miso", Pins("HPC:LA10_N")),
|
|
||||||
Subsignal("cs_n", Pins("HPC:LA11_N")),
|
|
||||||
IOStandard("LVDS_25")
|
|
||||||
),
|
|
||||||
("zotino_ldac", 0,
|
|
||||||
Subsignal("p", Pins("HPC:LA13_P")),
|
|
||||||
Subsignal("n", Pins("HPC:LA13_N")),
|
|
||||||
IOStandard("LVDS_25"), Misc("DIFF_TERM=TRUE")
|
|
||||||
)
|
|
||||||
]
|
|
||||||
|
|
||||||
|
|
||||||
# FMC DIO 32ch LVDS a v1.2 on HPC to VHDCI-Carrier v1.1
|
|
||||||
# uring the upper/right VHDCI connector: LVDS7 and LVDS8
|
|
||||||
# using the lower/left VHDCI connector: LVDS3 and LVDS4
|
|
||||||
_urukul = [
|
|
||||||
("urukul_spi_p", 0,
|
|
||||||
Subsignal("clk", Pins("HPC:LA17_CC_P")),
|
|
||||||
Subsignal("mosi", Pins("HPC:LA16_P")),
|
|
||||||
Subsignal("miso", Pins("HPC:LA24_P")),
|
|
||||||
Subsignal("cs_n", Pins("HPC:LA19_P HPC:LA20_P HPC:LA21_P")),
|
|
||||||
IOStandard("LVDS_25"),
|
|
||||||
),
|
|
||||||
("urukul_spi_n", 0,
|
|
||||||
Subsignal("clk", Pins("HPC:LA17_CC_N")),
|
|
||||||
Subsignal("mosi", Pins("HPC:LA16_N")),
|
|
||||||
Subsignal("miso", Pins("HPC:LA24_N")),
|
|
||||||
Subsignal("cs_n", Pins("HPC:LA19_N HPC:LA20_N HPC:LA21_N")),
|
|
||||||
IOStandard("LVDS_25"),
|
|
||||||
),
|
|
||||||
("urukul_io_update", 0,
|
|
||||||
Subsignal("p", Pins("HPC:LA22_P")),
|
|
||||||
Subsignal("n", Pins("HPC:LA22_N")),
|
|
||||||
IOStandard("LVDS_25"),
|
|
||||||
),
|
|
||||||
("urukul_dds_reset", 0,
|
|
||||||
Subsignal("p", Pins("HPC:LA23_P")),
|
|
||||||
Subsignal("n", Pins("HPC:LA23_N")),
|
|
||||||
IOStandard("LVDS_25"),
|
|
||||||
),
|
|
||||||
("urukul_sync_clk", 0,
|
|
||||||
Subsignal("p", Pins("HPC:LA18_CC_P")),
|
|
||||||
Subsignal("n", Pins("HPC:LA18_CC_N")),
|
|
||||||
IOStandard("LVDS_25"),
|
|
||||||
),
|
|
||||||
("urukul_sync_in", 0,
|
|
||||||
Subsignal("p", Pins("HPC:LA25_P")),
|
|
||||||
Subsignal("n", Pins("HPC:LA25_N")),
|
|
||||||
IOStandard("LVDS_25"),
|
|
||||||
),
|
|
||||||
("urukul_io_update_ret", 0,
|
|
||||||
Subsignal("p", Pins("HPC:LA26_P")),
|
|
||||||
Subsignal("n", Pins("HPC:LA26_N")),
|
|
||||||
IOStandard("LVDS_25"),
|
|
||||||
),
|
|
||||||
("urukul_sw0", 0,
|
|
||||||
Subsignal("p", Pins("HPC:LA28_P")),
|
|
||||||
Subsignal("n", Pins("HPC:LA28_N")),
|
|
||||||
IOStandard("LVDS_25"),
|
|
||||||
),
|
|
||||||
("urukul_sw1", 0,
|
|
||||||
Subsignal("p", Pins("HPC:LA29_P")),
|
|
||||||
Subsignal("n", Pins("HPC:LA29_N")),
|
|
||||||
IOStandard("LVDS_25"),
|
|
||||||
),
|
|
||||||
("urukul_sw2", 0,
|
|
||||||
Subsignal("p", Pins("HPC:LA30_P")),
|
|
||||||
Subsignal("n", Pins("HPC:LA30_N")),
|
|
||||||
IOStandard("LVDS_25"),
|
|
||||||
),
|
|
||||||
("urukul_sw3", 0,
|
|
||||||
Subsignal("p", Pins("HPC:LA31_P")),
|
|
||||||
Subsignal("n", Pins("HPC:LA31_N")),
|
|
||||||
IOStandard("LVDS_25"),
|
|
||||||
)
|
|
||||||
]
|
|
||||||
|
|
||||||
|
|
||||||
class _StandaloneBase(MiniSoC, AMPSoC):
|
class _StandaloneBase(MiniSoC, AMPSoC):
|
||||||
|
|
@ -243,8 +149,6 @@ class _StandaloneBase(MiniSoC, AMPSoC):
|
||||||
self.platform.add_extension(_sma33_io)
|
self.platform.add_extension(_sma33_io)
|
||||||
self.platform.add_extension(_ams101_dac)
|
self.platform.add_extension(_ams101_dac)
|
||||||
self.platform.add_extension(_sdcard_spi_33)
|
self.platform.add_extension(_sdcard_spi_33)
|
||||||
self.platform.add_extension(_zotino)
|
|
||||||
self.platform.add_extension(_urukul)
|
|
||||||
|
|
||||||
i2c = self.platform.request("i2c")
|
i2c = self.platform.request("i2c")
|
||||||
self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
|
self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
|
||||||
|
|
@ -340,37 +244,6 @@ class NIST_CLOCK(_StandaloneBase):
|
||||||
rtio_channels.append(rtio.Channel.from_phy(
|
rtio_channels.append(rtio.Channel.from_phy(
|
||||||
phy, ififo_depth=4))
|
phy, ififo_depth=4))
|
||||||
|
|
||||||
fmcdio_dirctl = self.platform.request("fmcdio_dirctl")
|
|
||||||
for s in fmcdio_dirctl.clk, fmcdio_dirctl.ser, fmcdio_dirctl.latch:
|
|
||||||
phy = ttl_simple.Output(s)
|
|
||||||
self.submodules += phy
|
|
||||||
rtio_channels.append(rtio.Channel.from_phy(phy))
|
|
||||||
|
|
||||||
sdac_phy = spi2.SPIMaster(self.platform.request("zotino_spi_p"),
|
|
||||||
self.platform.request("zotino_spi_n"))
|
|
||||||
self.submodules += sdac_phy
|
|
||||||
rtio_channels.append(rtio.Channel.from_phy(sdac_phy, ififo_depth=4))
|
|
||||||
|
|
||||||
pads = platform.request("zotino_ldac")
|
|
||||||
ldac_phy = ttl_serdes_7series.Output_8X(pads.p, pads.n)
|
|
||||||
self.submodules += ldac_phy
|
|
||||||
rtio_channels.append(rtio.Channel.from_phy(ldac_phy))
|
|
||||||
|
|
||||||
dac_monitor = ad53xx_monitor.AD53XXMonitor(sdac_phy.rtlink, ldac_phy.rtlink)
|
|
||||||
self.submodules += dac_monitor
|
|
||||||
sdac_phy.probes.extend(dac_monitor.probes)
|
|
||||||
|
|
||||||
phy = spi2.SPIMaster(self.platform.request("urukul_spi_p"),
|
|
||||||
self.platform.request("urukul_spi_n"))
|
|
||||||
self.submodules += phy
|
|
||||||
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
|
|
||||||
|
|
||||||
for signal in "io_update dds_reset sw0 sw1 sw2 sw3".split():
|
|
||||||
pads = platform.request("urukul_{}".format(signal))
|
|
||||||
phy = ttl_serdes_7series.Output_8X(pads.p, pads.n)
|
|
||||||
self.submodules += phy
|
|
||||||
rtio_channels.append(rtio.Channel.from_phy(phy))
|
|
||||||
|
|
||||||
phy = dds.AD9914(platform.request("dds"), 11, onehot=True)
|
phy = dds.AD9914(platform.request("dds"), 11, onehot=True)
|
||||||
self.submodules += phy
|
self.submodules += phy
|
||||||
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
|
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
|
||||||
|
|
|
||||||
|
|
@ -68,26 +68,6 @@ With the CLOCK hardware, the TTL lines are mapped as follows:
|
||||||
+--------------------+-----------------------+--------------+
|
+--------------------+-----------------------+--------------+
|
||||||
| 21 | LA32_P | Clock |
|
| 21 | LA32_P | Clock |
|
||||||
+--------------------+-----------------------+--------------+
|
+--------------------+-----------------------+--------------+
|
||||||
| 27 | FMCDIO_DIRCTL_CLK | Output |
|
|
||||||
+--------------------+-----------------------+--------------+
|
|
||||||
| 28 | FMCDIO_DIRCTL_SER | Output |
|
|
||||||
+--------------------+-----------------------+--------------+
|
|
||||||
| 29 | FMCDIO_DIRCTL_LATCH | Output |
|
|
||||||
+--------------------+-----------------------+--------------+
|
|
||||||
| 31 | ZOTINO_LDAC | Output |
|
|
||||||
+--------------------+-----------------------+--------------+
|
|
||||||
| 33 | URUKUL_IO_UPDATE | Output |
|
|
||||||
+--------------------+-----------------------+--------------+
|
|
||||||
| 34 | URUKUL_DDS_RESET | Output |
|
|
||||||
+--------------------+-----------------------+--------------+
|
|
||||||
| 35 | URUKUL_SW0 | Output |
|
|
||||||
+--------------------+-----------------------+--------------+
|
|
||||||
| 36 | URUKUL_SW1 | Output |
|
|
||||||
+--------------------+-----------------------+--------------+
|
|
||||||
| 37 | URUKUL_SW2 | Output |
|
|
||||||
+--------------------+-----------------------+--------------+
|
|
||||||
| 38 | URUKUL_SW3 | Output |
|
|
||||||
+--------------------+-----------------------+--------------+
|
|
||||||
|
|
||||||
The board has RTIO SPI buses mapped as follows:
|
The board has RTIO SPI buses mapped as follows:
|
||||||
|
|
||||||
|
|
@ -104,16 +84,9 @@ The board has RTIO SPI buses mapped as follows:
|
||||||
+--------------+------------------+--------------+--------------+------------+
|
+--------------+------------------+--------------+--------------+------------+
|
||||||
| 26 | MMC_SPI_CS_N | MMC_SPI_MOSI | MMC_SPI_MISO | MMC_SPI_CLK|
|
| 26 | MMC_SPI_CS_N | MMC_SPI_MOSI | MMC_SPI_MISO | MMC_SPI_CLK|
|
||||||
+--------------+------------------+--------------+--------------+------------+
|
+--------------+------------------+--------------+--------------+------------+
|
||||||
| 30 | ZOTINO_CS_N | ZOTINO_MOSI | ZOTINO_MISO | ZOTINO_CLK |
|
|
||||||
+--------------+------------------+--------------+--------------+------------+
|
|
||||||
| 32 | URUKUL_CS_N[0:2] | URUKUL_MOSI | URUKUL_MISO | URUKUL_CLK |
|
|
||||||
+--------------+------------------+--------------+--------------+------------+
|
|
||||||
|
|
||||||
The DDS bus is on channel 39.
|
The DDS bus is on channel 27.
|
||||||
|
|
||||||
This configuration supports a Zotino and/or an Urukul connected to the KC705 FMC HPC through a FMC DIO 32ch LVDS v1.2 and a VHDCI breakout board rev 1.0 or rev 1.1. On the VHDCI breakout board, the VHDCI cable to the KC705 should be plugged into to the bottom connector. The EEM cable to the Zotino should be connected to J41 and the EEM cables to Urukul to J42 and J43.
|
|
||||||
|
|
||||||
The shift registers on the FMC card should be configured to set the directions of its LVDS buffers, using :mod:`artiq.coredevice.shiftreg`.
|
|
||||||
|
|
||||||
NIST QC2
|
NIST QC2
|
||||||
++++++++
|
++++++++
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue