From 2e55e39ac7003bfbbae158cef333773841230498 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Thu, 28 Nov 2019 17:40:25 +0800 Subject: [PATCH] wrpll: use spaces to indent --- artiq/gateware/drtio/wrpll/core.py | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/artiq/gateware/drtio/wrpll/core.py b/artiq/gateware/drtio/wrpll/core.py index 4c2a35a91..d4a4435a7 100644 --- a/artiq/gateware/drtio/wrpll/core.py +++ b/artiq/gateware/drtio/wrpll/core.py @@ -6,16 +6,16 @@ from artiq.gateware.drtio.wrpll.si549 import Si549 class WRPLL(Module, AutoCSR): - def __init__(self, helper_clk_pads, main_dcxo_i2c, helper_dxco_i2c): - self.helper_reset = CSRStorage(reset=1) + def __init__(self, helper_clk_pads, main_dcxo_i2c, helper_dxco_i2c): + self.helper_reset = CSRStorage(reset=1) - self.clock_domains.cd_helper = ClockDomain() - self.helper_reset.storage.attr.add("no_retiming") - self.specials += [ - Instance("IBUFGDS", i_I=helper_clk_pads.p, i_IB=helper_clk_pads.n, - o_O=self.cd_helper.clk), - AsyncResetSynchronizer(self.cd_helper, self.helper_reset.storage) - ] + self.clock_domains.cd_helper = ClockDomain() + self.helper_reset.storage.attr.add("no_retiming") + self.specials += [ + Instance("IBUFGDS", i_I=helper_clk_pads.p, i_IB=helper_clk_pads.n, + o_O=self.cd_helper.clk), + AsyncResetSynchronizer(self.cd_helper, self.helper_reset.storage) + ] - self.submodules.main_dcxo = Si549(main_dcxo_i2c) - self.submodules.helper_dcxo = Si549(helper_dxco_i2c) + self.submodules.main_dcxo = Si549(main_dcxo_i2c) + self.submodules.helper_dcxo = Si549(helper_dxco_i2c)