From 2e39802a611701d6adb1ce3929bfa316e1704690 Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Thu, 10 Mar 2016 09:44:05 +0800
Subject: [PATCH] rtio/wishbone: make replace configurable

---
 artiq/gateware/rtio/phy/wishbone.py | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/artiq/gateware/rtio/phy/wishbone.py b/artiq/gateware/rtio/phy/wishbone.py
index 2e9d6bc4a..bff70ef84 100644
--- a/artiq/gateware/rtio/phy/wishbone.py
+++ b/artiq/gateware/rtio/phy/wishbone.py
@@ -5,7 +5,7 @@ from artiq.gateware.rtio import rtlink
 
 
 class RT2WB(Module):
-    def __init__(self, address_width, wb=None):
+    def __init__(self, address_width, wb=None, rtio_enable_replace=False):
         if wb is None:
             wb = wishbone.Interface()
         self.wb = wb
@@ -14,7 +14,7 @@ class RT2WB(Module):
                 len(wb.dat_w),
                 address_width + 1,
                 suppress_nop=False,
-                enable_replace=False),
+                enable_replace=rtio_enable_replace),
             rtlink.IInterface(
                 len(wb.dat_r),
                 timestamped=False)